I am unable to translate the 109 Gbps speed in C-PHY mode with the given number of physical lanes in AGX Xavier. It has 16 Data lanes (each with two wires Dn, Dp) and 8 clock lanes ( each with Cp/Cn) resulting in a total BW of 40 Gbps. I could not find the D-PHY (two wire lane) to C-PHY (3 wire lane with embedded clock) mapping which would lead to 109 Gbps.
We are still at the initial stage of shortlisting the right hardware architecture for reading 4 CSI-2 C-PHY 1.0 image sensors. We would need 58 Gbps from 4 sensors ( each with 3 Trios) and looks like AGX Xavier is one of the few options we have with a C-PHY physical layer with a huge bandwidth.
Any feedback ?