C-PHY interfacing in AGX Xavier

Hi Folks

I am unable to translate the 109 Gbps speed in C-PHY mode with the given number of physical lanes in AGX Xavier. It has 16 Data lanes (each with two wires Dn, Dp) and 8 clock lanes ( each with Cp/Cn) resulting in a total BW of 40 Gbps. I could not find the D-PHY (two wire lane) to C-PHY (3 wire lane with embedded clock) mapping which would lead to 109 Gbps.

We are still at the initial stage of shortlisting the right hardware architecture for reading 4 CSI-2 C-PHY 1.0 image sensors. We would need 58 Gbps from 4 sensors ( each with 3 Trios) and looks like AGX Xavier is one of the few options we have with a C-PHY physical layer with a huge bandwidth.

Any feedback ?


Hi, please refer to OEM DG, Xavier supports 2.5Gsps = 5.715(2.5x2.286) Gbps/Trio, which should be able cover your request.

Hi Trumany

So on the latest "NVIDIA Jetson AGX Xavier Series System-on-Module"version, I found “Corrected supported C-PHY operation (changed 2.5 Gsym/s to 1.7 Gsym/s)” revised on 27th August 2019 which i assume is the updated and correct number.

For both cases, the number of trios would be 19 (for 5.7 Gbps) and 28 (for 3.87 Gbps). What i also wish to know is regardless of the origin of 109 Gbps, how are the D-PHY wires mapped to C-PHY trios in NVCSI 2.0. I would think that there could be a max of 16 trios possible with 48 wires ( 16 - 2 wire data lane and 8 2 wire clock lane).

Are there block diagrams of NVCSI 2.0 which i was not able to find

thanks again

You can get the mapping info from OEM DG : https://developer.nvidia.com/embedded/dlc/jetson-agx-xavier-series-oem-product-design-guide

We are checking the symbol rate difference, will update once available, thanks.

Hi Trumany

Thank you very much for the pin mapping data. 4 x 4 lane (trio) C-PHY configuration looks good for 4 camera acquisition. Our image sensor/camera has 3 C-PHY lanes (trios) only. I assume it should be possible to use 4 cameras as 4x 3 lanes (trio).
Thanks for confirming the above and the symbol rate difference (whenever possible). Our image sensor is capable of 14 Gbps (30 fps) and hence we wish to use 3 C-PHY lanes (trios)

Result come out that it should be 1.7Gsps/Trio = 3.88 Gbps/Trio, 4 x 4 C-PHY configuration would be sufficient to your design.