How to use two NVCSI bricks to transfer only one stream for CPHY?

hello,dear support team:
I have a question about CPHY,
According to the Orin-TRM_DP10508002_v1.0p.pdf
1.1 Pixel Conveyances

Brick One instantiation of NVCSI; the hardware-managing lanes and links that are used. The D-PHY/C-PHY bricks have four lanes that can 
individually be configured into an x4 stream, an x2/x2 stream pair, an x2/x1 stream pair, or an x1/x1 stream pair. There are two D-PHY/C-PHY bricks that can use both streams in a pair, and two D-PHY/C-PHY bricks that have only one stream connected.

Does this mean that a CPHY can also receive only one stream by combining two bricks like a DPHY 8-lanes mode.If possible, what configuration do I need to do at the NVCSI SCIL level?

hello 541449841,

I don’t quite understand your question, may I know what’s the actual use-case? are you going to use DPHY or CPHY?

furthermore,
please download Jetson AGX Orin Series Design Guide (including AGX Orin Industrial).
you may check the diagrams, such as [Figure 10-1. Camera CSI D-PHY Connections] or, [Figure 10-2. Camera CSI C-PHY Connections] for reference.

hello Jerry
Thank you for your reply
We’re going to use C-PHY
We need to receive 6-trios data at least

hello 541449841,

may I also know the actual use-case, and the target data-rate?
FYI, we have not yet validate two brick merge approach on AGX Orin series.

We are a CMOS design company,Due to design limitations, we can only do 2.5Gsps/trio,
target stream should be16384x10920x12bit@15fps
Due to the limitations of our chip design capabilities,I know Orin supports to 4.5Gsps/trio,However, the CMOS sensor we designed can only emit MIPI signals with 2.5Gsps/trio。

hello 541449841,

we have reference CPHY sensor, (IMX318 based CPHY sensor) that’s validate up-to 1.06 Gsps.
for evaluation… our internal verification confirms that up-to 2.5 Gsps in C-PHY can be received with default CSI settings.

hence,
please go ahead to have a try, please gather logs if you bump into issues.
thanks

hello jerry
We have verified 3-trios under 16384x10920x12bit@7fps, @2.5Gsps
If we wanted to transfer 16384x10920x12bit@15fps, we would probably need 6-trios at least , so we would need two NVCSI bricks. What additional configuration does that require?The IMX318 sensor is only available in 3-trios reference configuration.

how to configure a CPHY using two NVCSI bricks,For example:
TRIO-1
CSI_A_D0_P —CPHY_A0_A
CSI_A_D0_N —CPHY_A0_B
CSI_A_CLK_P— CPHY_A0_C
TRIO-2
CSI_A_D1_P —CPHY_A1_A
CSI_A_D1_N— CPHY_A1_B
CSI_A_CLK_N— CPHY_A1_C
TRIO-3
CSI_B_D0_P— CPHY_B0_A
CSI_B_D0_N— CPHY_B0_B
CSI_B_CLK_P— CPHY_B0_C
TRIO-4
CSI_B_D1_P— CPHY_B1_A
CSI_B_D1_N— CPHY_B1_B
CSI_B_CLK_N— CPHY_B1_C
TRIO-5
CSI_C_D0_P— CPHY_C0_A
CSI_C_D0_N— CPHY_C0_B
CSI_C_CLK_P CPHY_C0_C
TRIO-6
CSI_C_D1_P —CPHY_C1_A
CSI_C_D1_N —CPHY_C1_B
CSI_C_CLK_N —CPHY_C1_C

hello 541449841,

this was supported on TX2 series, using two NVCSI bricks is done by VI drivers.
let me show the code-snippet as below.
$public_sources/kernel_src/kernel/nvidia/drivers/media/platform/tegra/camera/vi/channel.c

static int tegra_channel_csi_init(struct tegra_channel *chan)
{
...

        for (idx = 0; idx < TEGRA_CSI_BLOCKS && csi_port_is_valid(chan->port[idx]); idx++) {
                chan->total_ports++;
                /* maximum of 4 lanes are present per CSI block */
                chan->csibase[idx] = vi->iomem +
                                        TEGRA_VI_CSI_BASE(chan->port[idx]);
        }
        /* based on gang mode valid ports will be updated - set default to 1 */
        chan->valid_ports = chan->total_ports ? 1 : 0;

TX2 supported this due to bandwidth limitation, it needs to enable 4K by gang mode.
however,
we don’t really test merge CSI bricks since Xavier (and later) series have higher capability.

hello Jerry

Thank you very much for your reply, it seems to be exactly what I was looking for. So how do I use this gang mode? I see Orin SDK code also has a related implementation, we want to have a try,are there any relevant camera driver samples?

hello 541449841,

this is common VI driver, vi/channel.c,
Orin series use this VI operation drivers, vi/vi5_fops.c, whereas TX2 use this VI operation drivers, vi/vi4_fops.c
you may see-also TX2 codes for reference.

Ok, I will refer to the code of TX2. What I want to ask is does any sensor module on TX2 use gang mode? IMX318? IMX219 or whatever

it’s TC358840, HDMI2CSI bridge driver.

What we want to know is does gang mode also work with CPHY?

hello 541449841,

truth is… we did not test gang mode with CPHY sensors before.
it shall works, since it uses the common VI driver for operations.

1 Like

Sounds like good news. Could you please help with the testing of CPHY gang mode? This might be a little difficult for us, and will the use of gang mode involve some code that is not open source?

hello 541449841,

sorry, we don’t have device to test this locally.
as you can see in the Camera Architecture Stack. those code were public sources as long as you’re using v4l2 interface.

hello,Jerry
I have a question:

enum camera_gang_mode {
	CAMERA_NO_GANG_MODE = 0,
	CAMERA_GANG_L_R = 1,
	CAMERA_GANG_T_B,
	CAMERA_GANG_R_L,
	CAMERA_GANG_B_T
};

What do these camera_gang_mode represent, and which mode should I use

hello 541449841,

you may choose the mode depends-on your use-case,
let’s taking CAMERA_GANG_L_R as an example, that’s means left/right gang mode,
for such setting, it’s 1st CSI brick will fill the left region and 2nd CSI brick to fill the right region.

I got it,and how about the hardware connection for CPHY 2x3trios?
I guess it should be this:

1st CSI brick
{
  TRIO-1
  CSI_A_D0_P —CPHY_A0_A
  CSI_A_D0_N —CPHY_A0_B
  CSI_A_CLK_P— CPHY_A0_C
  TRIO-2
  CSI_A_D1_P —CPHY_A1_A
  CSI_A_D1_N— CPHY_A1_B
  CSI_A_CLK_N— CPHY_A1_C
  TRIO-3
  CSI_B_D0_P— CPHY_B0_A
  CSI_B_D0_N— CPHY_B0_B
  CSI_B_CLK_P— CPHY_B0_C
}
2nd CSI brick
{
  TRIO-4
  CSI_C_D0_P —CPHY_C0_A
  CSI_C_D0_N —CPHY_C0_B
  CSI_C_CLK_P— CPHY_C0_C
  TRIO-5
  CSI_C_D1_P —CPHY_C1_A
  CSI_C_D1_N— CPHY_C1_B
  CSI_C_CLK_N— CPHY_C1_C
  TRIO-6
  CSI_D_D0_P— CPHY_D0_A
  CSI_D_D0_N— CPHY_D0_B
  CSI_D_CLK_P— CPHY_D0_C
}