Couldn't receive camera data in CPHY mode

szcszc123 · February 20, 2025, 9:30am

Couldn’t receive camera data in CPHY mode.
There is an error. What’s the meaning of status:0x00000040?
kworker/4:4-505 [004] … 3574.748655: rtcpu_nvcsi_intr: tstamp:112448461987 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000040
kworker/4:4-505 [004] … 3574.804647: rtcpu_nvcsi_intr: tstamp:112449478555 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000040
kworker/4:4-505 [004] … 3574.804649: rtcpu_nvcsi_intr: tstamp:112449540468 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000040
kworker/4:4-505 [004] … 3574.804649: rtcpu_nvcsi_intr: tstamp:112450819592 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000040

carolyuu · February 20, 2025, 9:30am

Hi,

For the camera basic functionality first needs to check the device and driver configuration.
You can reference to below program guide for the detailed information of device tree and driver implementation.
https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/SD/CameraDevelopment/SensorSoftwareDriverProgramming.html?highlight=programing#sensor-software-driver-programming

Please refer to Applications Using V4L2 IOCTL Directly by using V4L2 IOCTL to verify basic camera functionality.
https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/SD/CameraDevelopment/SensorSoftwareDriverProgramming.html?highlight=programing#to-run-a-v4l2-ctl-test

Once confirm the configure and still failed below link help to get log and some information and some tips for debug.
https://elinux.org/Jetson/l4t/Camera_BringUp#Steps_to_enable_more_debug_messages

Thanks!

szcszc123 · February 20, 2025, 9:39am

I want to know the meaning of status:0x00000040.
I have run the following commands to trace.
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate

echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 2 > /sys/kernel/debug/camrtc/log-level
echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
echo > /sys/kernel/debug/tracing/trace
cat /sys/kernel/debug/tracing/trace

szcszc123 · February 20, 2025, 9:40am

The camera configuration is
root@yt12-desktop:/home/yt12# v4l2-ctl -d /dev/video0 --list-formats-ext
ioctl: VIDIOC_ENUM_FMT
Type: Video Capture

    [0]: 'RG12' (12-bit Bayer RGRG/GBGB)
            Size: Discrete 1920x1080
                    Interval: Discrete 0.033s (30.000 fps)

root@yt12-desktop:/home/yt12# media-ctl -p -d /dev/media0
Media controller API version 5.10.120

Media device information

driver tegra-camrtc-ca
model NVIDIA Tegra Video Input Device
serial
bus info
hw revision 0x3
driver version 5.10.120

Device topology

entity 1: 13e40000.host1x:nvcsi@15a00000- (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev0
pad0: Sink
← “as_test 2-0010”:0 [ENABLED]
pad1: Source
→ “vi-output, as_test 2-0010”:0 [ENABLED]
entity 4: as_test 2-0010 (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev1
pad0: Source
[fmt:SRGGB12_1X12/1920x1080 field:none colorspace:srgb]
→ “13e40000.host1x:nvcsi@15a00000-”:0 [ENABLED]
entity 6: vi-output, as_test 2-0010 (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video0
pad0: Sink
← “13e40000.host1x:nvcsi@15a00000-”:1 [ENABLED]

szcszc123 · February 20, 2025, 9:48am

I use 3 lanes in CPHY mode.
The DTS is:
i2c@3180000 {
#address-cells = <0x01>;
#size-cells = <0x00>;
iommus = <0x03 0x04>;
dma-coherent;
compatible = “nvidia,tegra234-i2c”;
reg = <0x00 0x3180000 0x00 0x100>;
nvidia,hw-instance-id = <0x02>;
interrupts = <0x00 0x1b 0x04>;
scl-gpio = <0x04 0x72 0x00>;
sda-gpio = <0x04 0x73 0x00>;
status = “okay”;
clock-frequency = <0x61a80>;
clocks = <0x02 0x32 0x02 0x66>;
clock-names = “div-clk\0parent”;
assigned-clocks = <0x02 0x32>;
assigned-clock-parents = <0x02 0x66>;
resets = <0x02 0x1e>;
reset-names = “i2c”;
dmas = <0x05 0x17 0x05 0x17>;
dma-names = “rx\0tx”;
nvidia,epl-reporter-id = <0x8052>;
phandle = <0x305>;

	raw_1@10 {
		compatible = "sensing,test";
		reg = <0x10>;
		devnode = "video0";
		physical_w = "3.680";
		physical_h = "2.760";
		sensor_model = "imx390";
		use_sensor_mode_id = "true";
		reset-gpios = <0x04 0x3b 0x00>;
		pwdn-gpios = <0x04 0xa0 0x00>;
		pwr-gpios = <0x04 0xa7 0x00>;					
		phandle = <0x664>;

		mode0 {
			vc_id = [30 00];
			mclk_khz = "24000";
			num_lanes = [33 00];
			tegra_sinterface = "serial_a";
			phy_mode = "CPHY";
			discontinuous_clk = "no";
			dpcm_enable = "false";
			cil_settletime = [30 00];
			lane_polarity = [30 00];
			active_w = "1920";
			active_h = "1080";
			mode_type = "bayer";
			pixel_phase = "rggb";
			csi_pixel_bit_depth = "12";
			dynamic_pixel_bit_depth = "12";
			readout_orientation = [30 00];
			line_length = "2200";
			inherent_gain = [31 00];
			mclk_multiplier = "6.1875";
			pix_clk_hz = "148500000";
			serdes_pix_clk_hz = "833333333";
			gain_factor = "10";
			min_gain_val = [30 00];
			max_gain_val = "300";
			step_gain_val = [33 00];
			default_gain = [30 00];
			min_hdr_ratio = [31 00];
			max_hdr_ratio = [31 00];
			framerate_factor = "1000000";
			min_framerate = "30000000";
			max_framerate = "30000000";
			step_framerate = [31 00];
			default_framerate = "30000000";
			exposure_factor = "1000000";
			min_exp_time = "59";
			max_exp_time = "33333";
			step_exp_time = [31 00];
			default_exp_time = "33333";
			embedded_metadata_height = [30 00];
		};

		ports {
			port@0 {
				reg = <0x00>;

				endpoint {
					vc_id = <0x00>;
					port-index = <0x00>;
					bus-width = <0x03>;
					remote-endpoint = <0x0b>;
					phandle = <0x31d>;
				};
			};
		};
	};

…
…
…

	nvcsi@15a00000 {
		compatible = "nvidia,tegra194-nvcsi";
		clocks = <0x02 0x51>;
		clock-names = "nvcsi";
		status = "okay";
		num-channels = <0x02>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		num-tpg-channels = <0x24>;
		phandle = <0x4c6>;

		channel@0 {
			reg = <0x00>;
			status = "okay";
			phandle = <0x4c7>;

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					reg = <0x00>;
					status = "okay";
					phandle = <0x4c8>;

					endpoint@0 {
						port-index = <0x00>;
						bus-width = <0x03>;
						remote-endpoint = <0x31d>;
						status = "okay";
						phandle = <0x0b>;
					};
				};

				port@1 {
					reg = <0x01>;
					status = "okay";
					phandle = <0x4c9>;

					endpoint@1 {
						remote-endpoint = <0x2b4>;
						status = "okay";
						phandle = <0x26d>;
					};
				};
			};
		};

…
…
…
tegra-capture-vi {
compatible = “nvidia,tegra-camrtc-capture-vi”;
nvidia,vi-devices = <0x26a 0x26c>;
nvidia,vi-mapping-size = <0x06>;
nvidia,vi-mapping = <0x00 0x00 0x01 0x00 0x02 0x01 0x03 0x01 0x04 0x00 0x05 0x01>;
nvidia,vi-mapping-names = “csi-stream-id\0vi-unit-id”;
nvidia,vi-max-channels = <0x48>;
num-channels = <0x02>;
phandle = <0x49d>;

	ports {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		port@0 {
			reg = <0x00>;
			status = "okay";
			phandle = <0x49e>;

			endpoint {
				vc-id = <0x00>;
				port-index = <0x00>;
				bus-width = <0x03>;
				remote-endpoint = <0x26d>;
				status = "okay";
				phandle = <0x2b4>;
			};
		};

…
…
…

tegra-camera-platform {
	compatible = "nvidia, tegra-camera-platform";
	num_csi_lanes = <0x03>;
	max_lane_speed = <0x16e360>;
	min_bits_per_pixel = <0x0a>;
	vi_peak_byte_per_pixel = <0x02>;
	vi_bw_margin_pct = <0x19>;
	isp_peak_byte_per_pixel = <0x05>;
	isp_bw_margin_pct = <0x19>;
	max_pixel_rate = <0xb71b0>;
	tpg_max_iso = <0x3bc400>;
	phandle = <0x53b>;

	modules {

		module0 {
			badge = "raw_1_bottom_A6V26";
			position = "bottom";
			orientation = [31 00];
			status = "okay";
			phandle = <0x53c>;

			drivernode0 {
				pcl_id = "v4l2_sensor";
				devname = "raw_1 30-0010";
				proc-device-tree = "/proc/device-tree/i2c@3180000/raw_1@10";
				status = "okay";
				phandle = <0x53d>;
			};

			drivernode1 {
				pcl_id = "v4l2_lens";
				proc-device-tree = "/proc/device-tree/lens_imx274@A6V26/";
				status = "okay";
				phandle = <0x53e>;
			};
		};

ShaneCCC · February 21, 2025, 4:57am

The log tell SOT(Start Of Transfer) error. That could be the timing issue.

szcszc123 · February 21, 2025, 6:30am

AGX use the Camera Connector interface.
I get the Jetson-AGX-Orin-Module-Carrier-Board-Specification_SP-10900-001_v1.2.pdf from Jetson Download Center | NVIDIA Developer
In the file there is only pin description.
Do you know how to connect pins in cphy mode？Do you know if AGX supports 3 lanes?

ShaneCCC · February 21, 2025, 6:43am

You can check the camera design guide.
Yes, CPHY 3 lanes configuration is supported.

szcszc123 · February 21, 2025, 7:19am

Do you know which pins are included in serial_a interface in CPHY 3 lanes configuration.
Perhaps CSI0_D0_P,CSI0_D0_N,CSI0_CLK_P,CSI0_CLK_N,CSI0_D1_P,CSI0_D1_N,CSI1_D0_P,CSI1_D0_N,CSI1_CLK_P,CSI1_CLK_N are included in serial_a interface in CPHY 3 lanes configuration. I am not sure.
I don’t find the definiton. Could you please share the link?

ShaneCCC · February 21, 2025, 7:45am

Right, it’s serial_a for CSI0 and the bus-width is 3 for 3 lanes.

szcszc123 · February 24, 2025, 8:37am

Do you know the meaning of every status bit in rtcpu_nvcsi_intr.

I find the CSI CPHY configuration in Jetson_AGX_Orin_Series_Data_Sheet_DS-10662-001_v1.5.pdf. But there is no CSI CPHY configuration of 3 lanes.
Do you know the CSI CPHY configuration of 3 lanes?

ShaneCCC · February 24, 2025, 10:14am

You can check the REG NVCSI_PHY_0_CILA_INTR_0_STATUS_CILA_0 in TRM download from download center.
Should be the same with 4 lanes configuration but don’t connect last like CSI0-CSI3 for 4 lanes then CSI0-CSI2 for 3 lanes.

Thanks

system · March 10, 2025, 10:14am

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.

Topic		Replies	Views
CPHY does not work , but DPHY can work ON same Hardware environment Jetson AGX Orin camera	32	1943	November 22, 2023
Jetson AGX Xavier 4 CSI RAW Input From FPGA Jetson AGX Xavier camera	64	1614	April 15, 2024
CPHY does not work using gst-launch (but works with v4l2) Jetson AGX Orin camera , gstreamer	24	1199	March 23, 2023
AGX开发板 + jetpack4.6+cpyh imx318 Jetson AGX Xavier camera	10	539	November 24, 2021
V4l2-ctl can't capture video data Jetson AGX Orin camera , board-design	44	3421	May 17, 2023
AGX开发板 + jetpack4.6+nvcsi CLK+cphy Jetson AGX Xavier hw	9	1283	December 8, 2021
How to configure MIPI CPHY at 3500 Msps Jetson AGX Orin camera	14	567	July 2, 2024
AGX Orin failed to capature image of cphy mode Jetson AGX Orin camera	39	1176	January 30, 2024
How do I fit a new sensor on driver orin? Jetson AGX Orin camera	21	1138	July 12, 2023
Jetson agx orin(32g&64g) cannot light up the camera successfully in cphy mode Jetson AGX Orin camera	4	156	June 24, 2024

Couldn't receive camera data in CPHY mode

Media device information

Related topics