Jetson agx orin(32g&64g) cannot light up the camera successfully in cphy mode

Hi,nv college
We had some problems while debugging the camera.

Software and hardware environment

Hardware: Jetson AGX Orin 64g&32g
Software :Jetson Linux 36.3(Jetson Linux 35.3.1 both)
Camera type: 8m(3840*2162 yuyv 30fps)
Interface:cphy 4*trio (test speed is 1.5g/per trio)

device tree:

i2c@3160000 {
di_cam_a@30 {
	compatible = "nvidia,ov8m";

	channel_id = <0>;
	reg = <0x30>;
	vr_id = <0>;
	devnode = "video0";
	/* Physical dimensions of sensor */
	physical_w = "15.0";
	physical_h = "12.5";

	sensor_model ="ov8m";

	/* Defines number of frames to be dropped by driver internally after applying */
	/* sensor crop settings. Some sensors send corrupt frames after applying */
	/* crop co-ordinates */

	/* Convert Gain to unit of dB (decibel) befor passing to kernel driver */
	use_decibel_gain = "true";
	delayed_gain = "true";

	/* enable CID_SENSOR_MODE_ID for sensor modes selection */

	mode0 {
		mclk_khz = "37125";
		num_lanes = "4";
		phy_mode = "CPHY";				
		tegra_sinterface = "serial_a";
		vc_id = "0";
		discontinuous_clk = "no";
		dpcm_enable = "false";
		cil_settletime = "0";
		dynamic_pixel_bit_depth = "8";
		csi_pixel_bit_depth = "8";
		mode_type = "yuv";
		pixel_phase = "yuyv";
		active_w = "3840";
		active_h = "2162";
		readout_orientation = "0";
		line_length = "4400";
		inherent_gain = "1";
		pix_clk_hz = "81000000";
		serdes_pix_clk_hz = "400000000";
		gain_factor = "10";
		min_gain_val = "0";
		max_gain_val = "480";
		step_gain_val = "3";
		default_gain = "0";
		min_hdr_ratio = "1";
		max_hdr_ratio = "1";
		framerate_factor = "1000000";
		min_framerate = "30000000";
		max_framerate = "30000000";
		step_framerate = "1";
		default_framerate = "30000000";
		exposure_factor = "1000000";
		min_exp_time = "30";
		max_exp_time = "660000";
		step_exp_time = "1";
		default_exp_time = "33334";
		embedded_metadata_height = "0";
	};
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			di_out0: endpoint {
				vc-id = <0>;
				port-index = <0>;
				bus-width = <4>;
				remote-endpoint = <&di_csi_in0>;
				};
			};
		};
	};

Hardware connection method:
简图

According to the above environment, it can be used normally in dphy mode, but it cannot be used in cphy mode. The difference in device tree is phy_mode, cphy or dphy.
Also according to the previous post, changed csi5_fops.c.
https://forums.developer.nvidia.com/t/how-can-i-change-jetson-orin-camera-cphy-csi-swizzle-register/230841
https://forums.developer.nvidia.com/t/cphy-does-not-work-but-dphy-can-work-on-same-hardware-environment/266874/15

	/* Lane polarity */
	if (!is_cphy) {
		unsigned int index = 0;
		for (index = 0; index < NVCSI_BRICK_NUM_LANES; index++)
			brick_config.lane_polarity[index] = (lane_polarity >> index) & (0x1);
	}else/*Added code*/
	{
		dev_info(csi->dev, "%s: set phy polarity based on maxin96712.\n",__func__);
		/*maxin 96712 cphy config*/
		brick_config.phy_mode = NVCSI_PHY_TYPE_CPHY;
		brick_config.lane_polarity[0] = NVCSI_CPHY_POLARITY_ABC;
		brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_BCA;
		brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_ABC;
		brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_BCA;
	}

The detailed process is as follows:
After correctly importing the correct camera driver, image and device tree, start Orin.In the /dev directory, we can find the video node

d@d-desktop:~$ ls -al /dev/video0 
crw-rw----+ 1 root video 81, 0  6月 19 11:18 /dev/video0

At the same time, we can use an oscilloscope to capture the waveform of mipi cphy on the max96712 side.
Execute the following command

v4l2-ctl --set-fmt-video=width=3840,height=2162,pixelformat=YUYV --set-ctrl bypass_mode=0 --stream-mmap -d /dev/video0

No pictures found
kernel log

[11689.522591] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11689.524466] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[11692.082523] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[11692.082546] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11692.084443] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[11694.642517] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[11694.642543] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11694.643952] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[11697.202223] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[11697.202243] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11697.203598] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[11699.762365] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[11699.762390] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11699.764335] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[11702.326128] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[11702.326152] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11702.327096] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[11704.882262] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[11704.882286] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[11704.883988] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

trace log

    kworker/10:2-181     [010] ....... 11769.665114: rtcpu_nvcsi_intr: tstamp:368457317821 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665115: rtcpu_nvcsi_intr: tstamp:368457318157 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665115: rtcpu_nvcsi_intr: tstamp:368457319892 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665115: rtcpu_nvcsi_intr: tstamp:368457320356 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665116: rtcpu_nvcsi_intr: tstamp:368457322191 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665116: rtcpu_nvcsi_intr: tstamp:368457322533 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665117: rtcpu_nvcsi_intr: tstamp:368457325390 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665117: rtcpu_nvcsi_intr: tstamp:368457326531 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665118: rtcpu_nvcsi_intr: tstamp:368457327916 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665118: rtcpu_nvcsi_intr: tstamp:368457327916 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665118: rtcpu_nvcsi_intr: tstamp:368457329521 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665119: rtcpu_nvcsi_intr: tstamp:368457329521 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665119: rtcpu_nvcsi_intr: tstamp:368457330442 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665120: rtcpu_nvcsi_intr: tstamp:368457332497 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
    kworker/10:2-181     [010] ....... 11769.665120: rtcpu_nvcsi_intr: tstamp:368457332838 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080

To locate the problem,In order to locate the problem, I queried the underlying registers of nvcsi.Of course, we also removed the register firewall when querying the register.


d@d-desktop:~$ sudo busybox devmem 0x15a04738
d@d-desktop:~$ sudo busybox devmem 0x15a04738
0x00000000
d@d-desktop:~$ sudo busybox devmem 0x15a04002
Bus error

The value read from is not as expected.0x15a04738 should be 0x1000.Why do some registers report bus errors?

sudo busybox devmem 0x15a04738 w 0x1000
d@d-desktop:~$ sudo busybox devmem 0x15a04738
0x00000000

The value has not changed.
Above is my debugging process

Questions:
1.What is the possible problem if it cannot be used?
2.Why is the register value inconsistent with the expected value and the register cannot be set?
3.Has nvidia tested the combination of ABC + BCA?

Thank you very much for your prompt attention to this issue. I look forward to hearing from you soon.

Maybe try one lane first.

Thanks

max96712 not support 1 trio mode.


Are there any other possible methods?

The address is incorrect, it’s 11ce0 instead of4738

15a11ce0: NVCSI_PHY_0_NVCSI_CIL_A_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a11de0: NVCSI_PHY_0_NVCSI_CIL_B_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a21ce0: NVCSI_PHY_1_NVCSI_CIL_A_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a21de0: NVCSI_PHY_1_NVCSI_CIL_B_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a31ce0: NVCSI_PHY_2_NVCSI_CIL_A_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a31de0: NVCSI_PHY_2_NVCSI_CIL_B_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a41ce0: NVCSI_PHY_3_NVCSI_CIL_A_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //
15a41de0: NVCSI_PHY_3_NVCSI_CIL_B_POLARITY_SWIZZLE_CTRL_0         = 0x00000000 //

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