CPHY does not work , but DPHY can work ON same Hardware environment

Harrison_zhu · September 19, 2023, 10:12am

Hi nvidia team:
When I use Orin debug sensor(imx390)+max96717+max96712. On phy_mode is “DPHY”, Orin can get video; but On phy_mode is “CPHY”, Orin not get anything.
On “DPHY” foundation, I set mode0 “phy_mode = “CPHY”;”

On max96712 driver: I set 96712 work on c-phy , and set lane_polarity value on csi5_fops.c.

When I run “v4l2-ctl --set-fmt-video=width=1920,height=1080,pixelformat=UYVY --set-ctrl bypass_mode=0 --stream-mmap -d /dev/video0” cmd, I can get mipi wave form by measuring the signal with an oscilloscope,;

But Orin get nothinng input.

My Orin version is R35.4.1(5.1.2).

what wrong I do. Please help . thanks!

ShaneCCC · September 20, 2023, 4:08am

What’s the CPHY clock? Did you verify with lower speed like 1.0 ~ 1.5 G
Does your HW DPHY/CPHY compatible? Please check the design guide for the detail.

Harrison_zhu · September 20, 2023, 7:25am

ShaneCCC :
Thank you for your reply！
My Hardware Design Source 《Jetson_AGX_Xavier_and_Orin_Series_Camera_Design_Guide_DG-09364-001_v1.5.pdf》file。

And On max96712 dirver, I set CPHY data rate/trio is 5.7Gbps/lane.

like this:
define MAX96712_PHY_CLK (0x20|0x19)
max96712_write_reg(&client->dev,0x415,MAX96712_PHY_CLK);
max96712_write_reg(&client->dev,0x418,MAX96712_PHY_CLK);
max96712_write_reg(&client->dev,0x41b,MAX96712_PHY_CLK);
max96712_write_reg(&client->dev,0x41e,MAX96712_PHY_CLK);

On DPHY mode use 2.5Gbps/lane, The same settings to register of max96712.

But Orin get anything from csi.

ShaneCCC · September 20, 2023, 8:32am

Did you check the trace log if more information to analysis it.

Thanks

Harrison_zhu · September 20, 2023, 10:18am

Hi ShaneCCC:
Thank you very much!
And I do next cmd .
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 2 > /sys/kernel/debug/camrtc/log-level
echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
echo > /sys/kernel/debug/tracing/trace

cat /sys/kernel/debug/tracing/trace

And I get the trace log file:
tracing.log (78.6 MB)

Now, I use ov5460 to test.
my dtsi is
tegra234-p3737-0000-camera-ncs-cphy-ov5640_imx390.dtsi (50.3 KB)

dmesg info is :

I can not get any data from max96712. please help me !!

ShaneCCC · September 21, 2023, 4:09am

The trace log tell the err_intr_cil_data_lane_ctrl_err0_a/err_intr_dphy_cil_clk_lane_ctrl_err_a could be the lane configure problem.

Thanks

Harrison_zhu · September 21, 2023, 4:23am

ShaneCCC:
Are you mean “cil_settletime” in mode0 set error!
What is your suggestion to set it to ?

ShaneCCC · September 21, 2023, 4:33am

Doesn’t matter with settletime. Could be POLARITY_SWIZZLE_CPHY* incorrect.

Harrison_zhu · September 21, 2023, 7:59am

Hi ShaneCCC :
Can you tell me where to set “POLARITY_SWIZZLE_CPHY” up？

I think it look like set “brick_config.lane_polarity” , so I set it from NVCSI_CPHY_POLARITY_ACB to NVCSI_CPHY_POLARITY_CBA, but Orin can not get mipi data.

switch(lane_pol) {
case NVCSI_CPHY_POLARITY_ACB:
dev_info(csi->dev, “ncs:: CPHY mode: change ABC → ACB\n”);
brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_ACB;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_ACB;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_ACB;
break;
case NVCSI_CPHY_POLARITY_BCA:
dev_info(csi->dev, “ncs:: CPHY mode: change ABC → BCA\n”);
brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_BCA;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_BCA;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_BCA;
break;
case NVCSI_CPHY_POLARITY_BAC:
dev_info(csi->dev, “ncs:: CPHY mode: change ABC → BAC\n”);
brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_BAC;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_BAC;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_BAC;
break;
case NVCSI_CPHY_POLARITY_CAB:
dev_info(csi->dev, “ncs:: CPHY mode: change ABC → CAB\n”);
brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_CAB;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_CAB;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_CAB;
break;
case NVCSI_CPHY_POLARITY_CBA:
dev_info(csi->dev, “ncs:: CPHY mode: change ABC → CBA\n”);
brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_CBA;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_CBA;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_CBA;
break;
default:
break;
}

So ,where is set POLARITY_SWIZZLE_CPHY* ?

thinks!

ShaneCCC · September 21, 2023, 8:30am

If you follow the design guide that could be compatible for CPHY and DPHY that shouldn’t need to configure the “brick_config.lane_polarity”
Beside the index should be from 0 - 3

Harrison_zhu · September 21, 2023, 9:39am

Is “POLARITY_SWIZZLE_CPHY1_A (control for lane 1): 010 = ABC to BCA” line to "brick_config.lane_polarity[1] " ?

But where I can do set NVCSI_PHY_0_NVCSI_CIL_A_POLARITY_SWIZZLE_CTRL_0 bit 13:11.

ShaneCCC · September 21, 2023, 10:39am

brick_config.lane_polarity[0 -1] for POLARITY_SWIZZLE_CPHY0_A
brick_config.lane_polarity[2 -3] for POLARITY_SWIZZLE_CPHY1_A

Harrison_zhu · September 21, 2023, 11:51am

Hi ShaneCCC:
I use next to set "NVCSI_PHY_0_NVCSI_CIL_A_POLARITY_SWIZZLE_CTRL_0 " bit [13:8] ;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_BCA;
brick_config.lane_polarity[3] = (brick_config.lane_polarity[3] << 3) + NVCSI_CPHY_POLARITY_ABC;
dev_info(csi->dev, “ncs:: CPHy mode: default 0x%04X\n”, brick_config.lane_polarity[3]);

Still unable to receive MIPI data, what wrong I done, Please help !

ShaneCCC · September 22, 2023, 1:47am

Which trio need polarity swizzle for your design?

Harrison_zhu · September 22, 2023, 2:49am

Hi ShaneCCC
Thank you for your help！

Next pdf file is my hardware design.
ORIN_cpy_2.pdf (28.0 KB)

help me to set Orin polarity swizzel, thanks!

ShaneCCC · September 22, 2023, 6:53am

Dose it connect to CSI0? What’s the port-index? Does it 3 lane configure?

Harrison_zhu · September 22, 2023, 6:58am

Yes connect CSI0 and port-index is “0” , 3lane(trio) .
{
1trio:
csi0_D0_P
csi0_D0_N
csi0_CLK_P
2trio:
csi0_D1_P
csi0_D1_N
csi0_CLK_N
3trio:
csi1_D0_P
csi1_D0_N
csi1_CLK_P
}

this is my sensor dtsi
tegra234-p3737-0000-camera-ncs-cphy-ov5640_imx390.txt (5.1 KB)

ShaneCCC · September 22, 2023, 7:26am

Could you remove below those configure to use default to confirm.

brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_ACB;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_ACB;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_ACB;

Harrison_zhu · September 22, 2023, 7:51am

Yes, Ido it now.
My code is :
default:
dev_info(csi->dev, “ncs:: CPHY mode: default change ABC → ABC\n”);
brick_config.lane_polarity[1] = NVCSI_CPHY_POLARITY_ABC;
brick_config.lane_polarity[2] = NVCSI_CPHY_POLARITY_ABC;
brick_config.lane_polarity[3] = NVCSI_CPHY_POLARITY_ABC;
break;

The dmesg is :
[ 64.483214] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[ 64.492382] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 64.502981] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 64.510758] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[ 64.521445] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: ncs::[csi5_stream_set_config] cil_settletime=26
[ 64.521448] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: ncs:: CPHY mode: default change ABC → ABC
[ 64.521450] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 64.529181] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[ 64.540010] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

And not get mipi data.

Harrison_zhu · September 25, 2023, 6:53am

Hi ShaneCCC:
Can you get me some help!
Thanks!

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CPHY does not work , but DPHY can work ON same Hardware environment

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