V4l2-ctl can't capture video data

Hello there,

We are trying to bring up the Cameras in our custom board with AGX Orin 32GB module and JetPack 5.0.2.

The following is our current configuration:

v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=5
[ 1282.811300] bwmgr API not supported
[ 1283.230978] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512
[ 1283.264259] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512
[ 1283.297565] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512
[ 1283.330913] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 512

Could you please help have a look and give us some advice?

Thanks

PS:

  • max9296 CSI port A lane clock: 1.5Ghz

  • Further debug show that max9296 EBBR was asserted, and 1 Link A decoding error was detected.

sudo i2ctransfer -f -y 34 w2@0x48 0x00 0x13 r1
0xde → ERRB asserted
sudo i2ctransfer -f -y 34 w2@0x48 0x01 0xfc r1
0x01
sudo i2ctransfer -f -y 34 w2@0x48 0x01 0x1a r1
0x62
sudo i2ctransfer -f -y 34 w2@0x48 0x00 0x22 r1
0x01 → 1 Link A decoding error detected
sudo i2ctransfer -f -y 34 w2@0x62 0x01 0x12 r1
0x8a

hello haibo.xu,

did the serdes chip sending deskew signal?
you may see-also developer guide for SerDes Pixel Clock section.
re-cap as below…

Skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.

BTW,
there’s changes to revise the camera init sequence, which also resolve deskew timeout failures.
please moving to the latest release (i.e. JP-5.1.1/l4t-r35.3.1) if that’s possible. thanks

Hi Jerry,

(1) Regards to the 1.5Gbps threshold, does it mean the date rate of single CSI lane(x1) or the total CSI lane(x4) of the deserializer?

(2) If the skew calibration is required, how to generate the calibration signal?

(3) The maximum output data rate from one IMX490 camera is 2880186030121.2=2314137600 ~ 2.3Gbps. For max9296 with 2 cameras, the maximum output date rate is ~4.6Gbps. So we chose the max9296 PHY1 CLK to 1.5Ghz(reg:0x320=0x2F) which providing a maximum of1.5G*4=6Gbps data rate.

Does the above configuration make sense?

Regards,
Haibo

hello haibo.xu,

it’s the data rate “to” the CSI brick. so, you should check the output data-rate of deserializer.
skew calibration is performed on the sensor side, camera firmware will continue to wait until deskew has done.

According to the Orin module datasheet, there are 4 MIPI CSI x4 bricks, if the 1.5G was the threshold for a brick with 4 CSI lanes, then each lane’s data rate threshold would be 1.5G/4=375M?

hello haibo.xu,

that’s incorrect, 1.5G was the threshold for skew calibration request.
deskew calibration is a must if data-rate > 1.5 Gbps, Else the camera firmware will continue to wait for deskew signal from the sensor side. it’ll enable pixel parser when deskew calibration has completed.

furthermore,
please see Jetson AGX Orin Series Module Data Sheet, for the [5.16 CSI Configurations] section.

In D-PHY mode, each data channel has peak bandwidth of up to 2.5 Gbps per lane.

Thanks for your reply!

Currently, we have only one camera (2880 *1860 * 30 * 12~2.3Gbps) attached to Orin through max9296 x4 CSI port. So the maximum data rate for each CSI lane is < 600Mbps which should not trigger deskew calibration?

Per your suggestion, I’ll try to upgrade our SDK to r35.3.1 this week. Meanwhile, could you help have a look at our camera parameter setting as listed in the attached dts file? especailly the parameters below:

active_w = “2880”;
active_h = “1860”;
line_length = “3160”;
pix_clk_hz = “189600000”;
serdes_pix_clk_hz = “500000000”;

Thanks!

you should keep only serdes_pix_clk_hz property since you’ve SerDes chip use-case.
please check developer guide for SerDes Pixel Clock section, and review the clock settings.

Hi Jerry,

According to the SerDes Pixel Clock section, the serdes_pix_clk_hz was calculated as

serdes_pix_clk_hz = (deserializer output data rate in hertz) * (number of CSI lanes) / (bits per pixel).

One question here is how to get the deserializer output data rate in hertz?
Does it mean the measured data rate from max9296 CSI x1 lane? Or the clock specified in max9296 PHY clock register?

define MAX9296_PHY1_CLK_ADDR 0x320
define MAX9296_PHY1_CLK 0x2C // CSI PHY1 output frequency in multiples of
100Mhz

Thanks!

hello haibo.xu,

it’s the measured output data rate from deserializer. incorrect serdes_pix_clk_hz settings sometime caused buffer overrun issues.

Thanks!

After modifying the max9296 CSI port A lane mapping (reg 0x333: 0x4E->0xE4), the max9296 EBBR signal was not asserted, and the Link A decoding error also disappeared.

But the video data still can’t be captured

v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=3
[ 54.776720] bwmgr API not supported
[ 55.225078] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072
[ 55.258343] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072
[ 55.291681] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072
[ 55.324981] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072

After enabling the trace for more information, the trace log show intr_stat_ph_ecc_multi_bit_err(packet header muti bit ecc error for DPHY).

# tracer: nop
#
# entries-in-buffer/entries-written: 870857/2609684 #P:8
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _—=> hardirq/softirq
# || / _–=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
v4l2-ctl-2442 [006] … 1523.442241: tegra_channel_open: vi-output, imx390 34-001b
v4l2-ctl-2442 [006] … 1523.461128: tegra_channel_set_power: imx390 34-001b : 0x1
v4l2-ctl-2442 [006] … 1523.461148: camera_common_s_power: status : 0x1
v4l2-ctl-2442 [006] … 1523.461184: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-2442 [006] … 1523.461188: csi_s_power: enable : 0x1
v4l2-ctl-2442 [006] … 1523.461382: tegra_channel_capture_setup: vnc_id 0 W 2880 H 1860 fmt c4
v4l2-ctl-2442 [006] … 1523.469936: tegra_channel_set_stream: enable : 0x1
v4l2-ctl-2442 [006] … 1523.484551: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-2442 [006] … 1523.484555: csi_s_stream: enable : 0x1
v4l2-ctl-2442 [006] … 1523.485177: tegra_channel_set_stream: imx390 34-001b : 0x1
##### CPU 4 buffer started ####
kworker/4:3-127 [004] … 1540.933846: rtcpu_nvcsi_intr: tstamp:48944382157 class:CORRECTABLE_ERR type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:3-127 [004] … 1540.933847: rtcpu_nvcsi_intr: tstamp:48944382701 class:GLOBAL type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:3-127 [004] … 1540.933847: rtcpu_nvcsi_intr: tstamp:48944382701 class:CORRECTABLE_ERR type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:3-127 [004] … 1540.933847: rtcpu_nvcsi_intr: tstamp:48944383282 class:GLOBAL type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:3-127 [004] … 1540.933848: rtcpu_nvcsi_intr: tstamp:48944383282 class:CORRECTABLE_ERR type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001

Could you give us some suggestions for the direction to debug? May it be caused by max9295/9296 CSI lane mapping mismatch?

Thanks!

hello haibo.xu,

according to the error data, flags=0, it shows CAPTURE_STATUS_FLAG_CHANNEL_IN_ERROR.
it means channel encountered an uncorrectable error and it must be reset.

please have a try for sending a reset signal on SerDes chip before s_stream().

please have a try for sending a reset signal on SerDes chip before s_stream().

Reset both max9295 and max9296?

Thanks!

Hi Jerry,

After adding soft reset(one-shot) to both max9295 and max9296 before s_stream(), it still can’t capture the video data. But this time, the trace data was a little different…

v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-coun t=5
[ 342.528083] bwmgr API not supported
[ 342.932832] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_d ata 131072
[ 342.965862] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_d ata 131072
[ 342.999304] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_d ata 131072
[ 343.032639] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_d ata 131072

cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 247446/247446 #P:8
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _—=> hardirq/softirq
# || / _–=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
kworker/4:2-129 [004] … 333.595630: rtcpu_string: tstamp:11214295210 id:0x04010000 str:" VM0 deactivating."
v4l2-ctl-2072 [007] … 342.496351: tegra_channel_open: vi-output, imx390 34-001b
v4l2-ctl-2072 [007] … 342.514675: tegra_channel_set_power: imx390 34-001b : 0x1
v4l2-ctl-2072 [007] … 342.514698: camera_common_s_power: status : 0x1
v4l2-ctl-2072 [007] … 342.514734: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00 000- : 0x1
v4l2-ctl-2072 [007] … 342.514740: csi_s_power: enable : 0x1
v4l2-ctl-2072 [007] … 342.514882: tegra_channel_capture_setup: vnc_id 0 W 2880 H 1860 fmt c4
v4l2-ctl-2072 [004] … 342.526264: tegra_channel_set_stream: enable : 0x1
v4l2-ctl-2072 [004] … 342.538336: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a0 0000- : 0x1
v4l2-ctl-2072 [004] … 342.538339: csi_s_stream: enable : 0x1
v4l2-ctl-2072 [004] … 342.538775: tegra_channel_set_stream: imx390 34-001b : 0x1
kworker/4:2-129 [004] … 342.559785: rtcpu_string: tstamp:11494900935 id:0x04010000 str:" VM0 activating."
kworker/4:2-129 [004] … 342.559787: rtcpu_vinotify_event: tstamp:11495387330 cch:0 vi:0
tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:367842304928 data:0x379d580010000000
kworker/4:2-129 [004] … 342.559788: rtcpu_vinotify_event: tstamp:11495387581 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:367842311360 data:0x0000000031000001
kworker/4:2-129 [004] … 342.559788: rtcpu_vinotify_event: tstamp:11495387833 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:367842371680 data:0x379d550010000000
kworker/4:2-129 [004] … 342.559788: rtcpu_vinotify_event: tstamp:11495388042 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:367842378624 data:0x0000000031000002
kworker/4:2-129 [004] … 342.951806: rtcpu_nvcsi_intr: tstamp:11506742085 class:GLOBAL ty pe:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:2-129 [004] … 342.951808: rtcpu_nvcsi_intr: tstamp:11506742085 class:CORRECTAB LE_ERR type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:2-129 [004] … 342.951809: rtcpu_nvcsi_intr: tstamp:11506742679 class:GLOBAL ty pe:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:2-129 [004] … 342.951809: rtcpu_nvcsi_intr: tstamp:11506742679 class:CORRECTAB LE_ERR type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:2-129 [004] … 342.951810: rtcpu_nvcsi_intr: tstamp:11506743268 class:GLOBAL ty pe:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001
kworker/4:2-129 [004] … 342.951810: rtcpu_nvcsi_intr: tstamp:11506743268 class:CORRECTAB LE_ERR type:STREAM_NOVC phy:0 cil:0 st:4 vc:0 status:0x00000001

haibo.xu,

this shows multi-bit error in the DPHY packet header.

please also refer to Jetson Virtual Channel with GMSL Camera Framework, please examine all those settings for sensor configurations.
also, are you able to probe the signaling? is the deserializer output MIPI signal follow the MIPI spec?

Hi Jerry,

Thanks for the suggestion!

I double checked the DTS configuration according to the GMSL Camera Framework and I can’t see any abnormal configures based on my knowledge.

Could you help have a look on the sensor configuration?
(Currently, only camera imx490a@1b was enabled)

Platform Device Tree

i2c@4 {
        reg = <4>;
        i2c-mux,deselect-on-exit;
        #address-cells = <1>;
        #size-cells = <0>;
        dser_4: max9296@48 {
                compatible = "maxim,max9296";
                reg = <0x48>;
                csi-mode = "2x4";
                max-src = <2>;
                reset-gpios = <&gpio_expander_24 4 GPIO_ACTIVE_HIGH>;
        };
        ser_4_prim: max9295_prim@40 {
                compatible = "maxim,max9295";
                reg = <0x40>;
                is-prim-ser;
        };
        ser_4_a: max9295_a@62 {
                compatible = "maxim,max9295";
                reg = <0x62>;
                nvidia,gmsl-dser-device = <&dser_4>;
        };
        ser_4_b: max9295_b@60 {
                compatible = "maxim,max9295";
                reg = <0x60>;
                nvidia,gmsl-dser-device = <&dser_4>;
        };
        imx490_a@1b {
                def-addr = <0x1a>;
                /* Define any required hw resources needed by driver */
                /* ie. clocks, io pins, power sources */
                clocks = <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>,
                                <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>;
                clock-names = "extperiph1", "pllp_grtba";
                mclk = "extperiph1";
                nvidia,gmsl-ser-device = <&ser_4_a>;
                nvidia,gmsl-dser-device = <&dser_4>;
        };
        imx490_b@1c {
                def-addr = <0x1a>;
                /* Define any required hw resources needed by driver */
                /* ie. clocks, io pins, power sources */
                clocks = <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>,
                                <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>;
                clock-names = "extperiph1", "pllp_grtba";
                mclk = "extperiph1";
                nvidia,gmsl-ser-device = <&ser_4_b>;
                nvidia,gmsl-dser-device = <&dser_4>;
        };
};

Module Device Tree - VI

tegra-capture-vi {
        num-channels = <12>; 
        ports { 
                port@8 {
                        reg = <8>;
                        imx490_vi_in8: endpoint {
                                vc-id = <0>;
                                port-index = <4>;
                                bus-width = <4>;
                                remote-endpoint = <&imx490_csi_out8>;
                        };      
                };      
                port@9 {
                        reg = <9>;
                        imx490_vi_in9: endpoint {
                                vc-id = <1>;
                                port-index = <4>;
                                bus-width = <4>;
                                remote-endpoint = <&imx490_csi_out9>;
                        };      
                };      
        }       
}

Module Device Tree - NVCSI

host1x@13e00000 {
    nvcsi@15a00000 {
        num-channels = <12>;
        #address-cells = <1>;
        #size-cells = <0>;

        channel@8 {
                reg = <8>;
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        port@0 {
                                reg = <0>;
                                imx490_csi_in8: endpoint@16 {
                                        port-index = <4>;
                                        bus-width = <4>;
                                        remote-endpoint = <&imx490_imx490_out8>;
                                };
                        };
                        port@1 {
                                reg = <1>;
                                imx490_csi_out8: endpoint@17 {
                                        remote-endpoint = <&imx490_vi_in8>;
                                };
                        };
                };
        };

        channel@9 {
                reg = <9>;
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        port@0 {
                                reg = <0>;
                                imx490_csi_in9: endpoint@18 {
                                        port-index = <4>;
                                        bus-width = <4>;
                                        remote-endpoint = <&imx490_imx490_out9>;
                                };
                        };
                        port@1 {
                                reg = <1>;
                                imx490_csi_out9: endpoint@19 {
                                        remote-endpoint = <&imx490_vi_in9>;
                                };
                        };
                };
        };
    }
}

Virtual Channel and GMSL

i2c@4 {
        imx490_a@1b {
                compatible = "sony,imx490";
                reg = <0x1b>;
                devnode = "video8";

                mode0 {/*mode IMX490_MODE_2880X1860_CROP_30FPS*/
                        num_lanes = "4";
                        tegra_sinterface = "serial_e";
                        vc_id = "0";
                        mode_type = "bayer";
                        pixel_phase = "rggb";
                        pix_clk_hz = "189600000";
                        serdes_pix_clk_hz = "300000000";
                };
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        port@0 {
                                reg = <0>;
                                imx490_imx490_out8: endpoint {
                                        vc-id = <0>;
                                        port-index = <4>;
                                        bus-width = <4>;
                                        remote-endpoint = <&imx490_csi_in8>;
                                };
                        };
                gmsl-link {
                        src-csi-port = "b";
                        dst-csi-port = "a";
                        serdes-csi-link = "a";
                        csi-mode = "1x4";
                        st-vc = <0>;
                        vc-id = <0>;
                        num-lanes = <4>;
                        streams = "ued-u1", "raw12";
                };
        };

        imx490_b@1c {
               compatible = "sony,imx490";

               reg = <0x1c>;
               devnode = "video9";

               mode0 {/*mode IMX490_MODE_2880X1860_CROP_30FPS*/
                       num_lanes = "4";
                       tegra_sinterface = "serial_e";
                       vc_id = "1";
                       mode_type = "bayer";
                       pixel_phase = "rggb";
                       line_length = "3160";
                       pix_clk_hz = "189600000";
                       serdes_pix_clk_hz = "300000000";
               };
               ports {
                       #address-cells = <1>;
                       #size-cells = <0>;
                       port@0 {
                               reg = <0>;
                               imx490_imx490_out9: endpoint {
                                       vc-id = <1>;
                                       port-index = <4>;
                                       bus-width = <4>;
                                       remote-endpoint = <&imx490_csi_in9>;
                               };
                       };
               };
               gmsl-link {
                       src-csi-port = "b";
                       dst-csi-port = "a";
                       serdes-csi-link = "b";
                       csi-mode = "1x4";
                       st-vc = <0>;
                       vc-id = <1>;
                       num-lanes = <4>;
                       streams = "ued-u1", "raw12";
               };
       };
}

tegra-camera-platform node

tegra-camera-platform {
        compatible = "nvidia, tegra-camera-platform";

        num_csi_lanes = <4>;
        max_lane_speed = <4000000>;
        min_bits_per_pixel = <10>;
        vi_peak_byte_per_pixel = <2>;
        vi_bw_margin_pct = <25>;
        isp_peak_byte_per_pixel = <5>;
        isp_bw_margin_pct = <25>;

        modules {
                module8 {
                        badge = "imx490_rear";
                        position = "rear";
                        orientation = "1";
                        drivernode0 {
                                /* Declare PCL support driver (classically known as guid)  */
                                pcl_id = "v4l2_sensor";
                                /* Driver v4l2 device name */
                                devname = "imx490 34-001b";
                                /* Declare the device-tree hierarchy to driver instance */
                                proc-device-tree = "/proc/device-tree/i2c@3160000/pca9547@70/i2c@4/imx490_a@1b";
                        };
                };
                module9 {
                        badge = "imx490_rear";
                        orientation = "1";
                        drivernode0 {
                                /* Declare PCL support driver (classically known as guid)  */
                                pcl_id = "v4l2_sensor";
                                /* Driver v4l2 device name */
                                devname = "imx490 34-001c";
                                /* Declare the device-tree hierarchy to driver instance */
                                proc-device-tree = "/proc/device-tree/i2c@3160000/pca9547@70/i2c@4/imx490_b@1c";
                        };
                };
        };
}

Thanks!

hello haibo.xu,

here doesn’t looks correct.

you may check below properties.
src-csi-port: Port at which sensor is connected to its serializer device.
dst-csi-port: Destination CSI port on the Jetson side, connected at deserializer.
serdes-csi-link: GMSL link sensor/serializer connected to sensor CSI node.

for your use-case, both of dst-csi-port and serdes-csi-link should mapping to CSI-E.
please have a try, thanks

Hi Jerry,

According to the Jetson SDK imx390 driver, the dst-csi-port and src-csi-port should be treat as 9295/9296 CSI port(A/B). The serdes-csi-link node was used to define 9296 GMSL Link A/B.

        err = of_property_read_string(gmsl, "dst-csi-port", &str_value);
        if (err < 0) {
                dev_err(dev, "No dst-csi-port found\n");
                goto error;
        }
        priv->g_ctx.dst_csi_port =
                (!strcmp(str_value, "a")) ? GMSL_CSI_PORT_A : GMSL_CSI_PORT_B;

        err = of_property_read_string(gmsl, "src-csi-port", &str_value);
        if (err < 0) {
                dev_err(dev, "No src-csi-port found\n");
                goto error;
        }
        priv->g_ctx.src_csi_port =
                (!strcmp(str_value, "a")) ? GMSL_CSI_PORT_A : GMSL_CSI_PORT_B;


        err = of_property_read_string(gmsl, "serdes-csi-link", &str_value);
        if (err < 0) {
                dev_err(dev, "No serdes-csi-link found\n");
                goto error;
        }
        priv->g_ctx.serdes_csi_link =
                (!strcmp(str_value, "a")) ?
                        GMSL_SERDES_CSI_LINK_A : GMSL_SERDES_CSI_LINK_B;

Please correct me if I was wrong.

Thanks!

hello haibo.xu,

what’s your board design, which CSI port on Jetson platform you’re used?
you may see-also max9296 GMSL deserializer driver, there’re differnet settings of CSI lane controls.

        switch(g_ctx->dst_csi_port) {
        case GMSL_CSI_PORT_A:
        case GMSL_CSI_PORT_D:
                lane_ctrl_addr = MAX9296_LANE_CTRL1_ADDR;
                break;
        case GMSL_CSI_PORT_B:
        case GMSL_CSI_PORT_E:
                lane_ctrl_addr = MAX9296_LANE_CTRL2_ADDR;
                break;
...