V4l2-ctl failed with "VIFALC_TDSTATE"

Jetpack: 5.0.2GA
Hardware: orin + rn6752
rn6752: output 4Lanes CSI, 1080p@25 fps, YUYV422 8Bit, mipi clock 324M Hz

Mipi data can be captured by oscilloscope, but i get “VIFALC_TDSTATE” in the trace log after
v4l2-ctl -V --set-fmt-video=width=1920,height=1080 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=camera.yuv -d /dev/video0
Is the dtsi configuration wrong?
Any ideas? Thank you.

  1. Logs with debug-camera-fw.7z

    kernel log

    Sep  8 10:11:29 nvidia-agx-orin kernel: [   52.696507] [RCE] NVCSILP clock rate = 408000000 Hz.
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.240742] bwmgr API not supported
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269937] [RCE] VM0 deactivating.VM0 activating.NVCSILP clock rate = 408000000 Hz.
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269941] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269943] [RCE] MIPI clock = 324000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269945] [RCE] ===== NVCSI Stream Configuration =====
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269947] [RCE] stream_id: PP 0, csi_port: PORT A
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269949] [RCE] Brick: PHY 0, Mode: D-PHY
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269951] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269953] [RCE] Clock information:
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269955] [RCE] MIPI clock rate: 324.00 MHz
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269957] [RCE] T_HS settle: 0, T_CLK settle: 0
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269959] [RCE] ======================================
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269961] [RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269963] [RCE] nvcsi_calc_ths_settle ths_settle 65
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269965] [RCE] nvcsi_calc_ths_settle ths_settle 65
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269967] [RCE] nvcsi_calc_ths_settle ths_settle 65
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269968] [RCE] nvcsi_calc_tclk_settle tclk_settle 75
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269973] [RCE] ISR PHY 0 CIL_A 0x8
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269976] [RCE] ISR PHY 0 CIL_B 0x80
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269978] [RCE] ISR PHY 0 CIL_A 0x44
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269980] [RCE] ISR PHY 0 CIL_B 0x44
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269982] [RCE] ISR PHY 0 CIL_A 0x44
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269984] [RCE] ISR PHY 0 CIL_B 0x44
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269986] [RCE] ISR PHY 0 CIL_A 0x44
    Sep  8 10:12:04 nvidia-agx-orin kernel: [   87.269988] [RCE] ISR PHY 0 CIL_B 0x44
    ......(repeat)
    Sep  8 10:12:06 nvidia-agx-orin kernel: [   89.804629] (NULL device *): vi_capture_control_message: NULL VI channel received
    Sep  8 10:12:06 nvidia-agx-orin kernel: [   89.812351] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
    Sep  8 10:12:06 nvidia-agx-orin kernel: [   89.823029] (NULL device *): vi_capture_control_message: NULL VI channel received
    Sep  8 10:12:06 nvidia-agx-orin kernel: [   89.830756] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
trace
        kworker/0:1-15      [000] ....    52.696484: rtcpu_string: tstamp:2327555680 id:0x04010000 str:"NVCSILP clock rate = 408000000 Hz.
    "
        kworker/0:1-15      [000] ....    52.696520: rtcpu_dbg_set_loglevel: tstamp:2327583858 old:0 new:2
        kworker/0:1-15      [000] ....    57.796491: rtcpu_string: tstamp:2486508443 id:0x04010000 str:"VM0 deactivating."
            v4l2-ctl-2388    [003] ....    86.813399: tegra_channel_open: vi-output, rn6752 2-002c
            v4l2-ctl-2388    [003] ....    86.822022: tegra_channel_set_power: rn6752 2-002c : 0x1
            v4l2-ctl-2388    [003] ....    86.822036: camera_common_s_power: status : 0x1
            v4l2-ctl-2388    [003] ....    87.225245: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
            v4l2-ctl-2388    [003] ....    87.225251: csi_s_power: enable : 0x1
            v4l2-ctl-2388    [003] ....    87.226499: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
            v4l2-ctl-2388    [003] ....    87.236213: tegra_channel_set_stream: enable : 0x1
            v4l2-ctl-2388    [003] ....    87.250589: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
            v4l2-ctl-2388    [003] ....    87.250591: csi_s_stream: enable : 0x1
            v4l2-ctl-2388    [003] ....    87.251035: tegra_channel_set_stream: rn6752 2-002c : 0x1
        kworker/0:1-15      [000] ....    87.269931: rtcpu_string: tstamp:3407710717 id:0x04010000 str:"VM0 activating."
        kworker/0:1-15      [000] ....    87.269933: rtcpu_string: tstamp:3407807460 id:0x04010000 str:"NVCSILP clock rate = 408000000 Hz.
    "
        kworker/0:1-15      [000] ....    87.269939: rtcpu_string: tstamp:3408317381 id:0x04010000 str:"tegra_nvcsi_stream_set_config(vm0, stream=0, csi"
        kworker/0:1-15      [000] ....    87.269940: rtcpu_string: tstamp:3408317482 id:0x04010000 str:"=0)
    "
        kworker/0:1-15      [000] ....    87.269942: rtcpu_string: tstamp:3408317853 id:0x04010000 str:"MIPI clock = 324000 kHz, tHS-SETTLE = 0, tCLK-SE"
        kworker/0:1-15      [000] ....    87.269943: rtcpu_string: tstamp:3408317954 id:0x04010000 str:"TTLE = 0
    "
        kworker/0:1-15      [000] ....    87.269945: rtcpu_string: tstamp:3408318164 id:0x04010000 str:"===== NVCSI Stream Configuration =====
    "
        kworker/0:1-15      [000] ....    87.269947: rtcpu_string: tstamp:3408318407 id:0x04010000 str:"stream_id: PP 0, csi_port: PORT A
    "
        kworker/0:1-15      [000] ....    87.269949: rtcpu_string: tstamp:3408318667 id:0x04010000 str:"Brick: PHY 0, Mode: D-PHY
    "
        kworker/0:1-15      [000] ....    87.269951: rtcpu_string: tstamp:3408318950 id:0x04010000 str:"Partition: CIL A, LP bypass: Enabled, Lanes: 4
    "
        kworker/0:1-15      [000] ....    87.269953: rtcpu_string: tstamp:3408319126 id:0x04010000 str:"Clock information:
    "
        kworker/0:1-15      [000] ....    87.269954: rtcpu_string: tstamp:3408319427 id:0x04010000 str:"MIPI clock rate: 324.00 MHz
    "
        kworker/0:1-15      [000] ....    87.269956: rtcpu_string: tstamp:3408319671 id:0x04010000 str:"T_HS settle: 0, T_CLK settle: 0
    "
        kworker/0:1-15      [000] ....    87.269958: rtcpu_string: tstamp:3408319895 id:0x04010000 str:"======================================
    "
        kworker/0:1-15      [000] ....    87.269960: rtcpu_string: tstamp:3408321424 id:0x04010000 str:"tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
    "
        kworker/0:1-15      [000] ....    87.269962: rtcpu_string: tstamp:3408328575 id:0x04010000 str:"nvcsi_calc_ths_settle ths_settle 65
    "
        kworker/0:1-15      [000] ....    87.269964: rtcpu_string: tstamp:3408328837 id:0x04010000 str:"nvcsi_calc_ths_settle ths_settle 65
    "
        kworker/0:1-15      [000] ....    87.269966: rtcpu_string: tstamp:3408329095 id:0x04010000 str:"nvcsi_calc_ths_settle ths_settle 65
    "
        kworker/0:1-15      [000] ....    87.269968: rtcpu_string: tstamp:3408329352 id:0x04010000 str:"nvcsi_calc_tclk_settle tclk_settle 75
    "
        kworker/0:1-15      [000] ....    87.269971: rtcpu_vinotify_event: tstamp:3408364807 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:109051563328 data:0x379d580010000000
        kworker/0:1-15      [000] ....    87.269971: rtcpu_vinotify_event: tstamp:3408364943 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:109051569760 data:0x0000000031000001
        kworker/0:1-15      [000] ....    87.269972: rtcpu_vinotify_event: tstamp:3408365099 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:109051625056 data:0x379d550010000000
        kworker/0:1-15      [000] ....    87.269972: rtcpu_vinotify_event: tstamp:3408365230 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:109051631584 data:0x0000000031000002
        kworker/0:1-15      [000] ....    87.269972: rtcpu_string: tstamp:3408601975 id:0x04010000 str:"ISR PHY 0 CIL_A 0x8
    "
        kworker/0:1-15      [000] ....    87.269975: rtcpu_nvcsi_intr: tstamp:3408601735 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000008
        kworker/0:1-15      [000] ....    87.269975: rtcpu_string: tstamp:3408602360 id:0x04010000 str:"ISR PHY 0 CIL_B 0x80
    "
        kworker/0:1-15      [000] ....    87.269977: rtcpu_nvcsi_intr: tstamp:3408601735 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
        kworker/0:1-15      [000] ....    87.269977: rtcpu_string: tstamp:3408676669 id:0x04010000 str:"ISR PHY 0 CIL_A 0x44
    "
        kworker/0:1-15      [000] ....    87.269979: rtcpu_nvcsi_intr: tstamp:3408676433 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000044
        kworker/0:1-15      [000] ....    87.269980: rtcpu_string: tstamp:3408677045 id:0x04010000 str:"ISR PHY 0 CIL_B 0x44
    "
        kworker/0:1-15      [000] ....    87.269981: rtcpu_nvcsi_intr: tstamp:3408676433 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000044
        kworker/0:1-15      [000] ....    87.269982: rtcpu_string: tstamp:3408677626 id:0x04010000 str:"ISR PHY 0 CIL_A 0x44
    "
        kworker/0:1-15      [000] ....    87.269983: rtcpu_nvcsi_intr: tstamp:3408677395 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000044
        kworker/0:1-15      [000] ....    87.269984: rtcpu_string: tstamp:3408677996 id:0x04010000 str:"ISR PHY 0 CIL_B 0x44
        ......(repeat)
  1. CSI port used
    图片

  2. dtsi config
    The trace log prints “MIPI clock rate: 324.00 MHz”, when i set pix_clk_hz to “162000000”.
    According to “CSI port used”, i set tegra_sinterface to “serial_a”.

tegra-capture-vi {
    num-channels = <1>;
    status = "okay";
    ports {
        #address-cells = <1>;
        #size-cells = <0>;
        port@0 {
            reg = <0>;
            status = "okay";
            rn6752_vi_in0: endpoint {
                status = "okay";
                port-index = <0>;
                bus-width = <4>;
                remote-endpoint = <&rn6752_csi_out0>;
            };
        };
    };
};

host1x@13e00000 {
    nvcsi@15a00000 {
        num-channels = <1>;
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        channel@0 {
            reg = <0>;
            status = "okay";
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    status = "okay";
                    rn6752_csi_in0: endpoint@0 {
                        status = "okay";
                        port-index = <0>;
                        bus-width = <4>;
                        remote-endpoint = <&rn6752_rn6752_out0>;
                    };
                };
                port@1 {
                    reg = <1>;
                    status = "okay";
                    rn6752_csi_out0: endpoint@1 {
                        status = "okay";
                        remote-endpoint = <&rn6752_vi_in0>;
                    };
                };
            };
        };
    };
};

i2c@3180000 {
    status = "okay";
    rn6752_a@2c {
        status = "okay";
        compatible = "rn,rn6752";

        reg = <0x2c>;
        devnode = "video0";

        /* Physical dimensions of sensor */
        physical_w = "15.0";
        physical_h = "12.5";

        sensor_model ="rn6752";
        /* Define any required hw resources needed by driver */
        /* ie. clocks, io pins, power sources */
        clocks = <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>,
        <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>;
        clock-names = "extperiph1", "pllp_grtba";
        mclk = "extperiph1";
        pwdn-gpios = <&tegra_main_gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
        reset-gpios = <&tegra_main_gpio CAM_PWDN GPIO_ACTIVE_HIGH>;

        post_crop_frame_drop = "0";

        /* Convert Gain to unit of dB (decibel) befor passing to kernel driver */
        use_decibel_gain = "true";

        /* if true, delay gain setting by one frame to be in sync with exposure */
        delayed_gain = "true";

        /* enable CID_SENSOR_MODE_ID for sensor modes selection */
        use_sensor_mode_id = "true";

        /* WAR to prevent banding by reducing analog gain. Bug 2229902 */
        limit_analog_gain = "true";

        mode0 {/*mode RN6752_MODE_1920X1080_25FPS*/
            mclk_khz = "24000";
            num_lanes = "4";
            tegra_sinterface = "serial_a";
            phy_mode = "DPHY";
            discontinuous_clk = "yes";
            dpcm_enable = "false";
            cil_settletime = "0";

            mode_type = "yuv";
            pixel_phase = "uyvy";
            csi_pixel_bit_depth = "16"; 
            dynamic_pixel_bit_depth = "16";

            active_w = "1920";
            active_h = "1080";
            readout_orientation = "0";
            line_length = "1920";
            inherent_gain = "1";

            mclk_multiplier = "6.75";
            pix_clk_hz = "162000000";  

            embedded_metadata_height = "0";

            gain_factor = "10";
            min_gain_val = "0"; /* 0dB */
            max_gain_val = "480"; /* 48dB */
            step_gain_val = "3"; /* 0.3 */
            default_gain = "0";
            min_hdr_ratio = "1";
            max_hdr_ratio = "1";

            framerate_factor = "1000000";
            min_framerate = "25000000"; /* 25 */
            max_framerate = "25000000"; /* 25 */
            step_framerate = "1";
            default_framerate= "25000000";

            exposure_factor = "1000000";
            min_exp_time = "30"; /* us */
            max_exp_time = "660000"; /* us */
            step_exp_time = "1";
            default_exp_time = "33334";/* us */
        };

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                rn6752_rn6752_out0: endpoint {
                    port-index = <0>;
                    bus-width = <4>;
                    remote-endpoint = <&rn6752_csi_in0>;
                };
            };
        };
    };
};

tegra-camera-platform {
    compatible = "nvidia, tegra-camera-platform";

    num_csi_lanes = <4>;
    max_lane_speed = <1500000>;
    min_bits_per_pixel = <10>;
    vi_peak_byte_per_pixel = <2>;
    vi_bw_margin_pct = <25>;

    isp_peak_byte_per_pixel = <5>;
    isp_bw_margin_pct = <25>;


    modules {
        module0 {
            badge = "rn6752_bottom_rn6752";
            position = "bottom";
            orientation = "0";
            drivernode0 {
                /* Declare PCL support driver (classically known as guid)  */
                pcl_id = "v4l2_sensor";
                /* Driver v4l2 device name */
                devname = "rn6752 30-002c"; 
                /* Declare the device-tree hierarchy to driver instance */
                proc-device-tree = "/proc/device-tree/i2c@3180000/rn6752_a@2c"; 
                status = "okay";
            };
        };
    };
};

I try to change “pix_clk_hz” to 324000000 74250000…, and add “set_mode_delay_ms”, the problem remains unchanged.
Add some other information

media-ctl info:

$ media-ctl -p -d /dev/media0
Media controller API version 5.10.104

Media device information
------------------------
driver          tegra-camrtc-ca
model           NVIDIA Tegra Video Input Device
serial          
bus info        
hw revision     0x3
driver version  5.10.104

Device topology
- entity 1: 13e40000.host1x:nvcsi@15a00000- (2 pads, 2 links)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
	pad0: Sink
		<- "rn6752 2-002c":0 [ENABLED]
	pad1: Source
		-> "vi-output, rn6752 2-002c":0 [ENABLED]

- entity 4: rn6752 2-002c (1 pad, 1 link)
            type V4L2 subdev subtype Sensor flags 0
            device node name /dev/v4l-subdev1
	pad0: Source
		[fmt:UYVY8_1X16/1920x1080 field:none colorspace:srgb]
		-> "13e40000.host1x:nvcsi@15a00000-":0 [ENABLED]

- entity 6: vi-output, rn6752 2-002c (1 pad, 1 link)
            type Node subtype V4L flags 0
            device node name /dev/video0
	pad0: Sink
		<- "13e40000.host1x:nvcsi@15a00000-":1 [ENABLED]

v4l2-ctl info:
v4l2-ctl -d /dev/video0 --list-formats-ext

ioctl: VIDIOC_ENUM_FMT
	Type: Video Capture

	[0]: 'UYVY' (UYVY 4:2:2)
		Size: Discrete 1920x1080
			Interval: Discrete 0.040s (25.000 fps)
	[1]: 'NV16' (Y/CbCr 4:2:2)
		Size: Discrete 1920x1080
			Interval: Discrete 0.040s (25.000 fps)
	[2]: 'UYVY' (UYVY 4:2:2)
		Size: Discrete 1920x1080
			Interval: Discrete 0.040s (25.000 fps)

$ v4l2-compliance -d /dev/video0

v4l2-compliance SHA: not available, 64 bits

Compliance test for tegra-video device /dev/video0:

Driver Info:
	Driver name      : tegra-video
	Card type        : vi-output, rn6752 2-002c
	Bus info         : platform:tegra-capture-vi:0
	Driver version   : 5.10.104
	Capabilities     : 0x84200001
		Video Capture
		Streaming
		Extended Pix Format
		Device Capabilities
	Device Caps      : 0x04200001
		Video Capture
		Streaming
		Extended Pix Format
Media Driver Info:
	Driver name      : tegra-camrtc-ca
	Model            : NVIDIA Tegra Video Input Device
	Serial           : 
	Bus info         : 
	Media version    : 5.10.104
	Hardware revision: 0x00000003 (3)
	Driver version   : 5.10.104
Interface Info:
	ID               : 0x03000008
	Type             : V4L Video
Entity Info:
	ID               : 0x00000006 (6)
	Name             : vi-output, rn6752 2-002c
	Function         : V4L2 I/O
	Pad 0x01000007   : 0: Sink
	  Link 0x0200000c: from remote pad 0x1000003 of entity '13e40000.host1x:nvcsi@15a00000-': Data, Enabled

Required ioctls:
	test MC information (see 'Media Driver Info' above): OK
	test VIDIOC_QUERYCAP: OK

Allow for multiple opens:
	test second /dev/video0 open: OK
	test VIDIOC_QUERYCAP: OK
	test VIDIOC_G/S_PRIORITY: OK
	test for unlimited opens: OK

Debug ioctls:
	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
	test VIDIOC_LOG_STATUS: OK

Input ioctls:
	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
	test VIDIOC_ENUMAUDIO: OK (Not Supported)
	test VIDIOC_G/S/ENUMINPUT: OK
	test VIDIOC_G/S_AUDIO: OK (Not Supported)
	Inputs: 1 Audio Inputs: 0 Tuners: 0

Output ioctls:
	test VIDIOC_G/S_MODULATOR: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_ENUMAUDOUT: OK (Not Supported)
	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
	test VIDIOC_G/S_AUDOUT: OK (Not Supported)
	Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
	test VIDIOC_G/S_EDID: OK (Not Supported)

Control ioctls (Input 0):
	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
	test VIDIOC_QUERYCTRL: OK
	test VIDIOC_G/S_CTRL: OK
	test VIDIOC_G/S/TRY_EXT_CTRLS: OK
	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
	Standard Controls: 1 Private Controls: 22

Format ioctls (Input 0):
		fail: v4l2-test-formats.cpp(280): duplicate format 59565955 (UYVY)
	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: FAIL
		fail: v4l2-test-formats.cpp(1280): ret && node->has_frmintervals
	test VIDIOC_G/S_PARM: FAIL
	test VIDIOC_G_FBUF: OK (Not Supported)
	test VIDIOC_G_FMT: OK
	test VIDIOC_TRY_FMT: OK
	test VIDIOC_S_FMT: OK
	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
	test Cropping: OK (Not Supported)
	test Composing: OK (Not Supported)
	test Scaling: OK (Not Supported)

Codec ioctls (Input 0):
	test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
	test VIDIOC_G_ENC_INDEX: OK (Not Supported)
	test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

Buffer ioctls (Input 0):
		fail: v4l2-test-buffers.cpp(715): q.create_bufs(node, 1, &fmt) != EINVAL
	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: FAIL
	test VIDIOC_EXPBUF: OK
	test Requests: OK (Not Supported)

This seems similar to the problem I have, also the same fails with v4l2 compliance.
@ShaneCCC, do you know if we could have any other verified and working driver code which deals with yuv data as reference so that we can check if our device trees and driver code are correct?

Link to my forum post for reference in case any information there is helpful for you @nkpyq

Looks like the SOT error.
Maybe the timing issue. Have a confirm the timing like below. Make sure the SOT at reasonable place.

@ShaneCCC Thank you for your reply, I’ll get confirmation.
I’m confused about “pix_clk_hz” setting, I think this problem will also arise when CLK is wrong.
The following is my current setting. Will it conflict with #sensor-pixel-clock

Another setting that confuses me is format.
Why are three formats listed as below, and the listed formats [0] and [2] are the same. Can I directly specify to use MEDIA_BUS_FMT_UYVY8_2X8.

@bala.krishnan.gk
Thank you for your suggestion. Have you solved this problem?

  1. Suppose the MIPI clock = pix_clk_hz*pixel_depth
    2.It could be the sensor driver report problem.

Hi nkpyq,

unfortunately it’s still an on-going issue for us. There seem to be some issues with the CSI signal we are getting with our interface board when connected with the Orin.

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