If your point is correct, then devkit’s design clearly does not adhere to the routing guideline in DG, and our baseboard, which strictly adheres to the routing guideline in DG, does not work properly.
so please continue to answer my questions above:
Q1: Has Orin nano SOM’s MIPI wiring been adapted for 4lane applications, and the length of MIPI combined signal wires theoretically adapted for 4lane was adjusted to the same length between pairs during hardware design? For example, CSI2_CLK/D0/D1+CSI3_D0/D1, are the cable lengths of each difference pair are equal？
Q3: Has the 2.5G 4lane MIPI reception been officially tested on the J21?
Q4: What is the reason for the significantly longer CSI3_D0/D1 line for devkit?
Unfortunately, our design strictly followed the follow routing guideline, but it can’t work properly.
I have submitted the design file in the previous reply.
If possible, please review it and point out if there is anything out of compliance with the design guideline, thank you.
In addition, please reply to the questions I mentioned earlier, one by one.
We don’t provide review support in general as we have released design guide, checklist sheet and reference schematic. The failure on this could be caused by multi factor and since 2.5G rate had been validated before ship out, it should be some design issue on custom board. Please check that based on the docs we released.
On that note, I would like to know what baseboards you use to test SOM? Is it the devkit I mentioned earlier? Or another tooling board? CSI2_CLK/D0/D1+CSI3_D0/D1 on the test board, are the cable lengths of each difference pair are equal?
Please leave devkit questions along as it has nothing to do with custom design. Lots of customers had maken successful design based on the guide and reference. You may need to try to debug from other angle.
I just want to know your test situation of 2.5G 4lane MIPI, and the test conditions based on which the conclusion of PASS is reached.
In addition, can you provide SOM MIPI network layout line length table?
Let’s talk about the guide for the trace length.
In fact, the design guide does not specify how much line length should be achieved for each lane MIPI difference pair.
It only indicates that the delay between DQ/CLK and the maximum lengthshould be controlled.
Therefore, we have specially measured the waveform of MIPI signal near SOM for different situations, and found that it cannot work when the delay between DQ/CLK is less than 16ps, and it can work when the delay between DQ/CLK is about 50ps.
Note that delay is the only variable in the two test states, what’s your opinion on this?
If you do not understand the information I described above, can you ask your colleagues related to hardware designer step in and look at the relevant information?
I don’t think you really understand the DG. There is no need to request trace length of each lane again since max length and delay skew b/w Data and CLK are requested.
Regarding the failure on 16ps or 50ps, as said, it could be caused by many factors like your PCB routing impedance, signal noise and etc. And I really don’t undertand why you still focus on devkit questions. The spec in guide have been validated and used by many other customers, please don’t waste time on this and try to debug from other angles.
As for the impedance and noise you mentioned, I said before that the difference in delay is the only variable, which does not change other things.
We also tested the impedance, looked at the waveform, including the S-parameter, and found no anomalies.
What I said about the problem of 16ps/50ps is only by describing the phenomenon, hoping to obtain a more appropriate investigation direction.
I think I am asking the question here in the hope of getting your help to get the direction of analysis/solution.
By the way, I haven’t talked about devkit for a long time, so let’s get over it.
Absolutely yes, most of the questions I have mentioned have not received any positive answers so far.
We are trying to plug the module into devkit testing and decide on the next attempt based on the results.
The next step may be to design and verify the MIPI unequal length for our baseboard. Of course, this cycle will be relatively long. If there is any conclusive progress, I will update it in this topic.
We dont have other suggestion than that in the Design Guide, checklist sheet and reference design docs. For custom board design, please well follow those docs like other customers did no matter what the test result on devkit is.
