CSI D-PHY Design Guidelines - NVIDIA Jetson Xav ier OEM Product Design Guide (Solved)

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

It said: Signal Requirement is
Max Intra-pair Skew 1 ps
Max Trace Delay Skew between DQ & CLK 5 ps

This number seems too strict in 2.5Gbps or 400ps UI world.
Are those right?

2

Yes, please follow design guide.

3

In MIPI D-PHY Dynamic Data to Clock Skew Window RX Tolerance is minimum 0.5UI. It will be 200ps at 2.5Gbps.
It requires maximum 5ps still?

4

This skew is for PCB, in fact there is other skew in chip. The total skews are following D-PHY request.