CSI-2 interface cable

Hello,

In the framework of a project, I want to integrate a NVIDIA Xavier developer kit carrier board as an interface to collect MIPI signal from a custom sensor. I have to use two CSI-2 lanes and a CSI-2 CLK at a bandwidth of 1.5 Gbps.

In the jetson Xavier Developer Kit carrier Board specification (pg 27), a maximum trace delay of 450.27 ps is advised for the sensor carrier board, which is equivalent to only a few cm of trace on our pcb.

Will it be possible to use a microcoax cable between the sensor carrier board and the camera interposer module ? I’ve seen applications that use such cables over dozens of centimeters. Considering the length of the cable way longer than the PCB trace, how can I ensure that a 1.5 Gbps MIPI transmission to the Jetson Xavier can be handled with no risk ?
What interface (cables, connector) would you advise for relatively long distances (up to 50 cm) between the sensor carrier board and the camera interposer module?

Thank you for your answer and your time

hello agrohw,

according to Jetson AGX Xavier Software Features, please refer to CSI and USB Camera Features.
you’ll need [GMSL Camera and VC Support] for long distances signal transmit.

it’s a sensor module that use Serializer/Deserializer chips, please access L4T Sources to check reference drivers.
you may also check below drivers to demonstrate sensors with SerDes chips.
$l4t-r32.2/public_sources/kernel/nvidia/drivers/media/i2c/imx390.c
$l4t-r32.2/public_sources/hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi

please contact with Jetson Preferred Partners for camera solutions.
thanks

Thank you for your answer,

I still wonder something.

MIPI specifies that the flight time between two D-PHY interconnects should not exceed 2 ns, which is equivalent to around 25-30 cm for PCB/flex material trace length. However, referring to my previous post, the trace delay is only of 450.27 ps for PCB/flex material trace length. Why is this value significantly smaller than the MIPI requirements ?

Because the trace delay is only for carrier board design, there exist other trace on module board and chip.