Hi
I was wondering what shall be the correct procedures for PCB traceslength matching when designing the board to be plunged with Xavier AGX module?
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are anywhere available information about the trace lengths/trace delay in the Xavier AGX module itself (from Xavier Soc to the mezzanine connector) ? …I’ve searched whole documentation and haven’t found anything
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There are simulation models available (Jetson_AGX_Xavier_Sparameters_IBIS_Models.zip ), but they are all relevant only to SoC and does not take the module in consideration => are then quite useless. Or did I missed something?
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In production design guide (Jetson_AGX_Xavier_OEM_Product_Design_Guide) are some relevant information for trace length/delays, but again they seemed to be referenced to the SoC and not the mezzanine connector of the module => so cannot be used
ie. making one practical example. I want to route RGMII and Jetson_AGX_Xavier_OEM_Product_Design_Guide has requirement “Max Trace Length/Delay 175 (1200) mm (ps) See Note 3” and note 3 is “Include Package & PCB routing delays for Max trace delays and max trace delay skew parameters”. How shall I work with this when I don’t know anything about the routing on the Xavier module PCB ?
Many thanks
Daniel