Length matching to Xavier AGX module

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
#1

Hi

I was wondering what shall be the correct procedures for PCB traceslength matching when designing the board to be plunged with Xavier AGX module?

  1. are anywhere available information about the trace lengths/trace delay in the Xavier AGX module itself (from Xavier Soc to the mezzanine connector) ? …I’ve searched whole documentation and haven’t found anything

  2. There are simulation models available (Jetson_AGX_Xavier_Sparameters_IBIS_Models.zip ), but they are all relevant only to SoC and does not take the module in consideration => are then quite useless. Or did I missed something?

  3. In production design guide (Jetson_AGX_Xavier_OEM_Product_Design_Guide) are some relevant information for trace length/delays, but again they seemed to be referenced to the SoC and not the mezzanine connector of the module => so cannot be used

ie. making one practical example. I want to route RGMII and Jetson_AGX_Xavier_OEM_Product_Design_Guide has requirement “Max Trace Length/Delay 175 (1200) mm (ps) See Note 3” and note 3 is “Include Package & PCB routing delays for Max trace delays and max trace delay skew parameters”. How shall I work with this when I don’t know anything about the routing on the Xavier module PCB ?

Many thanks
Daniel

#2

Hi, the OEM DG guidelines are from the module pins on the carrier board to the device or connector on the carrier board. The full budget from chip to end device/connector was broken into the portion allowed on the module, and the portion allowed on the carrier board. The OEM DG max trace lengths are only the portion on the carrier board. That “Note 3” is wrong, will be removed in new release, thanks for your finding.

#3

Hi.

Many thanks for fast response.

back to my original question - part 2) The provided simulation files are then relevant also to the module connector or not?

Thx
Daniel

#4

Sure it is for module.

#5

Ok, Many thanks for answer.

I might also suggest updating the naming of the simulation files as “Xavier_SoC_IBIS_Models.zip”, “SDIO_RBMII_SPI_QSPI\Xavier_SoC_S1_142_82888_rgmii_r1_0000001.s47p” ,etc. looks like it’s related just to SoC and not whole module :-)