Question about PCIE tace length

Hi,We need to evaluate the length of the PCIE trace,so can you provide the information below

  1. the max trace length—from soc to molex connector.
    2.Maximum insertion loss that NV module can be tolerated.

Please find the info in Xavier product design guide in DLC: https://developer.nvidia.com/embedded/downloads

Hi,
Still can’t find the information after read the 6.2.1
Can you directly provide the information below?
1.the max trace length—from soc to molex connector.
2.Maximum insertion loss that NV module can be tolerated.

Please check PCIe chapter 7.2.1

Is that means the maximum insertion loss is 4.9dB?

That is trace loss, you can take it as a total value of trace loss plus insertion loss.