Hi NV Support Team
From “Jetson_AGX_Orin_Design_Guide_DG-10653-001_v1.0.pdf” Table 6-26
The max trace delay is 106mm. Trace Loss Budget 4.6dB @5.5GHz only for Jetson Orin to PHY.
Because we need to use XFI connection 2xJetson AGX Orin in my board. But as we don’t have Jetson AGX Orin module S-parameter and IBIS data .
So can you please help give the trace delay and trace budget for 2xOrin Moduel connection.
Below it is the requirment.
It is same for two Orin connection.
Some confuse as the design guidelin note5: In case extra connector or devices are add in the patch then the max trace length and insertion loss should be re-evaluated.
From my query: we add the 2nd Jetson orin module that means the whole channel loss will increased, because the additional 2nd CVM 669pin connector & PCB trace &Via&AC CAP in 2nd Jetson orin module.
So why the insertion loss or trace length are same as the before as your mention.
BTW: can you please provide Jetson Orin S-parameters and IBIS to me for PCB simulation.
Hi, sorry for misunderstanding your question. You can get the module delay by the Design Guide and XFI spec and then get what you should apply in the design. What you need is to obey the whole delay request of XFI port.
All released docs are included in DLC, please check there. If no such doc exists, please wait for release.
I can’t find the XFI signal (include trace, via ,connector pin)from Jetson orin moduel info in design guide.
Can you please show the screenshot?
The module docs are not public.
Jetson Orin 10G use 10GBASE-R protocol? So we need follow up XFI electrical interface rules. Which version XFI spec we need follow up ?
Do you think in our two orin module connection concept, do we need use 10G BASE-KR electrical interface rules?
As listed in DG: 6.4.2 MGBE Design Guidelines
The guidelines provided below apply mainly to XFI (or SFI) interface operating at 10.3125 Gbps data rate. Although overly conservative, these guidelines also apply to 5,15625 Gbps data rate as well.
If I dont know Orin module ( SoC+Trace+Via+Connector) S-parameters data,
I don’t think i can get the detail pcb loss/ delay in my two orin moduel connection design.
Ad you DG said :In case extra connector or devices are add in the patch then the max trace length and insertion loss should be re-evaluated.
Just follow the DG to make the carrier board. It can cover the routing request.
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