Jetson-Agx-Orin RGMII Interface build failed

likhithbabu.n · February 28, 2025, 12:11pm

Hi,

I’m trying to change the tegra234-p3737-0000.dtsi for RGMII Interface as per the Nvidia Documentation. but getting build fail.
phy-mode = “rgmii-id”;
phy-handle = <$phy>;
nvidia,phy-reset-gpio = <$tegra_main_gpio TEGRA234_MAIN_GPIO(g, $) 0>

mdio {
compatible = “nvidia,eqos-mdio”;
#address-cells = <1>;
#size-cells = <0>;

phy: phy@1 {
    reg = <1>;
    nvidia,phy-rst-pdelay-msec = <224>; /* msec */
    nvidia,phy-rst-duration-usec = <10000>; /* usec */
    interrupt-parent = <$tegra_main_gpio>;
    interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;

};
};
Trying to modifying in the below section in the file
ethernet@6800000 {
status = “okay”;

		phy-handle = <$phy>;
		phy-mode = "rgmii-id";
		nvidia,phy-reset-gpio = <$tegra_main_gpio TEGRA234_MAIN_GPIO(g, $) 0>

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			phy: phy@1{
				compatible = "nvidia,eqos-mdio";
				reg = <1>;
				nvidia,phy-rst-pdelay-msec = <224>; /* msec */
				nvidia,phy-rst-duration-usec = <10000>; /* usec */
				interrupt-parent = <$tegra_main_gpio>;
				interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
				#phy-cells = <0>;
			};
		};
	};

but getting the syntax Errors.

likhithbabu.n · March 1, 2025, 10:57am

I Have ressolved the error by

                phy-handle = <&phy>;
		phy-mode = "rgmii-id";
		nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			phy: phy@1{
				compatible = "nvidia,eqos-mdio";
				reg = <1>;
				nvidia,phy-rst-pdelay-msec = <224>; /* msec */
				nvidia,phy-rst-duration-usec = <10000>; /* usec */
				interrupt-parent = <&gpio>;
				interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
				#phy-cells = <0>;
			};
		};
	};

but when i tried to test the ethernet connectivity using the command ifconfig not listed with eth0 why ?

WayneWWW · March 4, 2025, 3:25am

HI,

RGMII change should be applied to 2310000 but not 6800000. 6800000 is for MGBE but not RGMII.

Also, pinmux change is needed.

likhithbabu.n · March 4, 2025, 6:13am

tegra234-mb1-bct-gpio-p3701-0000.dtsi.txt (4.8 KB)
tegra234-p3737-0000+p3701-0000.dts.txt (10.6 KB)
tegra234-mb1-bct-pinmux-p3701-0000.dtsi (63.6 KB)

ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,hsio-uphy-config-0,nvhs-uphy-config-0,”;

Hi,
I have modified the pinmux, kernel dts file as per the document.
but getting the below log when i tesed

ifconfig

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10
loop txqueuelen 1000 (Local Loopback)
RX packets 235 bytes 16523 (16.5 KB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 235 bytes 16523 (16.5 KB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

usb0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500
ether 82:c9:0d:7b:a5:d5 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

usb1: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500
ether 82:c9:0d:7b:a5:d7 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

sudo dmesg | grep -i phy

[ 9.024997] tegra194-pcie 14100000.pcie: Phy link never came up
[ 10.024800] tegra194-pcie 14100000.pcie: Phy link never came up
[ 10.280861] nvethernet 6800000.ethernet: failed to read UPHY GBE mode- default to 10G
[ 11.209377] tegra194-pcie 14160000.pcie: Phy link never came up
[ 12.211191] tegra194-pcie 14160000.pcie: Phy link never came up
[ 13.436795] tegra194-pcie 141a0000.pcie: Phy link never came up
[ 13.793844] nvethernet 6800000.ethernet: failed to connect PHY
[ 13.793853] net eno1: ether_open: Cannot attach to PHY (error: -19)
[ 14.424858] tegra194-pcie 141

Can you please let me if any changes require ?

WayneWWW · March 4, 2025, 6:58am

Is there any problem to understand this comment?

RGMII change should be applied to 2310000 but not 6800000. 6800000 is for MGBE but not RGMII.

Also, you should attach full log but not just those partial log. Your partial log does not provide any useful info.
If you don’t know what is useful info, you should not parse any log by yourself.

likhithbabu.n · March 4, 2025, 7:14am

ethernet boot log 4-02-25.txt (79.2 KB)
Can you please find the attached file for the boot log and ifconfig commad.

WayneWWW · March 4, 2025, 7:15am

You totally didn’t enable RGMII node at all.

likhithbabu.n · March 4, 2025, 8:37am

ethernet@2310000 is not available in the tegra234-p3737-0000+p3701-0000.dts file it’s available in nv-soc/tegra234-base-overlay.dtsi
can you please let me know to enable the RGMII, should i need to create the new node ethernet@2310000 in tegra234-p3737-0000+p3701-0000.dts or it is ok if i change the ethernet@6800000 to ethernet@2310000 .

WayneWWW · March 4, 2025, 8:57am

Hi,

Do not change ethernet@6800000 to ethernet@2310000… they are totally different things there. Doing that would just lead to crash.

tegra234-base-overlay.dtsi is the right location to add that.

likhithbabu.n · March 4, 2025, 9:27am

should i need to add the DT entries for RGMII in this node ?ethernet@2310000 {
compatible = “nvidia,nveqos”;
reg = <0x0 0x02310000 0x0 0x10000>, /* EQOS Base Register /
<0x0 0x023D0000 0x0 0x10000>, / MACSEC Base Register /
<0x0 0x02300000 0x0 0x10000>; / HV Base Register /
reg-names = “mac”, “macsec-base”, “hypervisor”;
interrupts = <0 194 0x4>, / common /
<0 186 0x4>, / vm0 /
<0 187 0x4>, / vm1 /
<0 188 0x4>, / vm2 /
<0 189 0x4>, / vm3 /
<0 190 0x4>, / MACsec non-secure intr /
<0 191 0x4>; / MACsec secure intr /
interrupt-names = “common”, “vm0”, “vm1”, “vm2”, “vm3”,
“macsec-ns-irq”, “macsec-s-irq”;
resets = <&bpmp TEGRA234_RESET_EQOS>,
<&bpmp TEGRA234_RESET_EQOS_MACSEC>; / MACsec non-secure reset /
reset-names = “mac”, “macsec_ns_rst”;
clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
<&bpmp TEGRA234_CLK_EQOS_AXI>,
<&bpmp TEGRA234_CLK_EQOS_RX>,
<&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
<&bpmp TEGRA234_CLK_EQOS_TX>,
<&bpmp TEGRA234_CLK_AXI_CBB>,
<&bpmp TEGRA234_CLK_EQOS_RX_M>,
<&bpmp TEGRA234_CLK_EQOS_RX_INPUT>,
<&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>,
<&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
<&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
clock-names = “pllrefe_vcoout”, “eqos_axi”, “eqos_rx”,
“eqos_ptp_ref”, “eqos_tx”, “axi_cbb”,
“eqos_rx_m”, “eqos_rx_input”,
“eqos_macsec_tx”, “eqos_tx_divider”,
“eqos_macsec_rx”;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
<&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
interconnect-names = “dma-mem”, “write”;
endif
iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
nvidia,num-dma-chans = <8>;
nvidia,num-mtl-queues = <8>;
nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
/ Residual Queue can be any valid queue except RxQ0 /
nvidia,residual-queue = <1>;
nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
nvidia,vm-irq-config = <&eqos_vm_irq_config>;
status = “disabled”;
nvidia,dcs-enable = <0x1>;
nvidia,macsec-enable = <0>;
nvidia,pad_calibration = <0x1>;
/ pad calibration 2’s complement offset for pull-down value /
nvidia,pad_auto_cal_pd_offset = <0x0>;
/ pad calibration 2’s complement offset for pull-up value /
nvidia,pad_auto_cal_pu_offset = <0x0>;
nvidia,rx_riwt = <512>;
nvidia,rx_frames = <64>;
nvidia,tx_usecs = <256>;
nvidia,tx_frames = <5>;
nvidia,promisc_mode = <1>;
nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
nvidia,ptp_ref_clock_speed = <208333334>;
nvidia,instance_id = <4>; / EQOS instance */
nvidia,ptp-rx-queue = <3>;
pinctrl-names = “mii_rx_disable”, “mii_rx_enable”;
pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
pinctrl-1 = <&eqos_mii_rx_input_state_enable>;
nvidia,dma_rx_ring_sz = <1024>;
nvidia,dma_tx_ring_sz = <1024>;
dma-coherent;
};
which is in the tegra234-base-overlay.dtsi file ?

WayneWWW · March 4, 2025, 9:29am

Yes… add DT entries to ethernet@2310000. If something already exist, then just modify it… no need to add again.

likhithbabu.n · March 4, 2025, 11:30am

thank you ,
even though if i update the file like this

mdio {
compatible = “nvidia,eqos-mdio”;
#address-cells = <1>;
#size-cells = <0>;

			phy: phy@1 {
				     reg = <1>;
				     nvidia,phy-rst-pdelay-msec = <224>; /* msec */
				     nvidia,phy-rst-duration-usec = <10000>; /* usec */
				     interrupt-parent = <&gpio>;
				     interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;

        					 };
		};

	ethernet@2310000 {
	
		status = "okay";
		compatible = "nvidia,nveqos";
		reg = <0x0 0x02310000 0x0 0x10000>,    /* EQOS Base Register */
		    <0x0 0x023D0000 0x0 0x10000>,    /* MACSEC Base Register */
		    <0x0 0x02300000 0x0 0x10000>;    /* HV Base Register */
		reg-names = "mac", "macsec-base", "hypervisor";
		interrupts = <0 194 0x4>,       /* common */
			   <0 186 0x4>, /* vm0 */
			   <0 187 0x4>, /* vm1 */
			   <0 188 0x4>, /* vm2 */
			   <0 189 0x4>, /* vm3 */
			   <0 190 0x4>, /* MACsec non-secure intr */
			   <0 191 0x4>; /* MACsec secure intr */
		interrupt-names = "common", "vm0", "vm1", "vm2", "vm3",
			"macsec-ns-irq", "macsec-s-irq";
		resets = <&bpmp TEGRA234_RESET_EQOS>,
		       <&bpmp TEGRA234_RESET_EQOS_MACSEC>; /* MACsec non-secure reset */
		reset-names = "mac", "macsec_ns_rst";
		clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
		       <&bpmp TEGRA234_CLK_EQOS_AXI>,
		       <&bpmp TEGRA234_CLK_EQOS_RX>,
		       <&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
		       <&bpmp TEGRA234_CLK_EQOS_TX>,
		       <&bpmp TEGRA234_CLK_AXI_CBB>,
		       <&bpmp TEGRA234_CLK_EQOS_RX_M>,
		       <&bpmp TEGRA234_CLK_EQOS_RX_INPUT>,
		       <&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>,
		       <&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
		       <&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
		clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx",
			"eqos_ptp_ref", "eqos_tx", "axi_cbb",
			"eqos_rx_m", "eqos_rx_input",
			"eqos_macsec_tx", "eqos_tx_divider",
			"eqos_macsec_rx";
		phy-mode = "rgmii-id";
		phy-handle = <&phy>;
		nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;

#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
<&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
interconnect-names = “dma-mem”, “write”;
endif
iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
nvidia,num-dma-chans = <8>;
nvidia,num-mtl-queues = <8>;
nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
/* Residual Queue can be any valid queue except RxQ0 */
nvidia,residual-queue = <1>;
nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
nvidia,vm-irq-config = <&eqos_vm_irq_config>;
/*status = “disabled”; /
nvidia,dcs-enable = <0x1>;
nvidia,macsec-enable = <0>;
nvidia,pad_calibration = <0x1>;
/ pad calibration 2’s complement offset for pull-down value /
nvidia,pad_auto_cal_pd_offset = <0x0>;
/ pad calibration 2’s complement offset for pull-up value /
nvidia,pad_auto_cal_pu_offset = <0x0>;
nvidia,rx_riwt = <512>;
nvidia,rx_frames = <64>;
nvidia,tx_usecs = <256>;
nvidia,tx_frames = <5>;
nvidia,promisc_mode = <1>;
nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
nvidia,ptp_ref_clock_speed = <208333334>;
nvidia,instance_id = <4>; / EQOS instance */
nvidia,ptp-rx-queue = <3>;
pinctrl-names = “mii_rx_disable”, “mii_rx_enable”;
pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
pinctrl-1 = <&eqos_mii_rx_input_state_enable>;
nvidia,dma_rx_ring_sz = <1024>;
nvidia,dma_tx_ring_sz = <1024>;
dma-coherent;

};

no changes happened same as previous.

WayneWWW · March 5, 2025, 2:04am

Shared your dmesg again… no one can just tell what is going on by just reading this…

Also, please stop “copy and paste” the whole codes on the forum. It is a disaster to do that. Please attach it as file.

likhithbabu.n · March 5, 2025, 9:15am

OK
I’m sharing the boot log along with tried commands after the changed made.
Now I’m able to see the eth1 but it not up when trying to make it up

WayneWWW · March 5, 2025, 9:20am

Please attach your full dmesg as text log. Do not share screenshot or parse anything.

The original text log is always the best one.

likhithbabu.n · March 5, 2025, 9:20am

eth_bootlog.txt (75.9 KB)

WayneWWW · March 5, 2025, 9:24am

[ 16.502974] nvethernet 2310000.ethernet: failed to connect PHY
[ 16.502984] net eth1: ether_open: Cannot attach to PHY (error: -19)

Probably to have a hardware problem here.

likhithbabu.n · March 5, 2025, 9:32am

can you please once confirm the modified dtsi file is correct as per the changes done.
tegra234-base-overlay.dtsi.txt (19.6 KB)

WayneWWW · March 5, 2025, 9:37am

Why do you put the mdio in a weird location that is not under RGMII node?

likhithbabu.n · March 5, 2025, 9:42am

when trying to put it under the RGMII node getting the build error
So tried by putting the handle inside the RGMII node and mdio to
outside

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Jetson-Agx-Orin RGMII Interface build failed

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