ORIN RGMII can not LINK (phy 88e1512P)

xianfei.chen · July 31, 2023, 6:48am

https://docs.nvidia.com/jetson/archives/r35.2.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=rgmii#for-rgmii

xianfei.chen · July 31, 2023, 6:52am

HI NV TEAM
We designed a carrier board for Orin.The RGMII interface is used,and the PHY chip is 88E1512.
We did the following:
ethernet@2310000 {
status = “okay”;
//nvidia,if-name = “EQOS”;
nvidia,mac-addr-idx = <0>;
local-mac-address = [1a 2b 3c 4d 5e 6f];
nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
phy-mode = “rgmii-id”;
phy-handle = <&phy>;
///delete-node/ fixed-link;
nvidia,max-platform-mtu = <8000>;
fixed-link{
speed = <1000>;
full-duplex;
};

	mdio {
		compatible = "nvidia,eqos-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		phy: phy@1 {
			//compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			nvidia,phy-rst-pdelay-msec = <224>; // msec
			nvidia,phy-rst-duration-usec = <10000>; // usec 
			interrupt-parent = <&tegra_main_gpio>;
			interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
			marvell,copper-mode;
			marvell,reg-init=<0x03 0x12 0x7ff 0x880>;
		};
	};
};

WayneWWW · July 31, 2023, 8:34am

This is not needed.

fixed-link{
speed = <1000>;
full-duplex;
};

WayneWWW · July 31, 2023, 8:36am

Check the document for the pinmux setting.

https://docs.nvidia.com/jetson/archives/r35.3.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=rgmii#for-rgmii

xianfei.chen · July 31, 2023, 9:18am

eqos_txc_pe0 {
nvidia,pins = “eqos_txc_pe0”;
nvidia,function = “eqos”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};

		eqos_td0_pe1 {
			nvidia,pins = "eqos_td0_pe1";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td1_pe2 {
			nvidia,pins = "eqos_td1_pe2";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td2_pe3 {
			nvidia,pins = "eqos_td2_pe3";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td3_pe4 {
			nvidia,pins = "eqos_td3_pe4";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_tx_ctl_pe5 {
			nvidia,pins = "eqos_tx_ctl_pe5";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

eqos_rd0_pe6 {
nvidia,pins = “eqos_rd0_pe6”;
nvidia,function = “eqos”;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};

		eqos_rd1_pe7 {
			nvidia,pins = "eqos_rd1_pe7";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd2_pf0 {
			nvidia,pins = "eqos_rd2_pf0";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd3_pf1 {
			nvidia,pins = "eqos_rd3_pf1";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rx_ctl_pf2 {
			nvidia,pins = "eqos_rx_ctl_pf2";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rxc_pf3 {
			nvidia,pins = "eqos_rxc_pf3";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_sma_mdio_pf4 {
			nvidia,pins = "eqos_sma_mdio_pf4";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_sma_mdc_pf5 {
			nvidia,pins = "eqos_sma_mdc_pf5";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

soc_gpio17_pg4 {
nvidia,pins = “soc_gpio17_pg4”;
nvidia,function = “rsvd0”;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

		soc_gpio18_pg5 {
			nvidia,pins = "soc_gpio18_pg5";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
		};

xianfei.chen · July 31, 2023, 9:19am

hi nvidia team
I configured it based on the reference document，Looks like there’s no problem

xianfei.chen · August 1, 2023, 1:56am

Do you have any suggestions？

WayneWWW · August 1, 2023, 3:11am

麻煩你確認一下flash log. 看一下pinmux真的是預期燒進去的檔案
看一下/proc/interrupts 裡面ethernet的interrupt數字有沒有增加

xianfei.chen · August 1, 2023, 4:16am

root@lcfc-desktop:/home/lcfc# cat /proc/interrupts | grep eth
68: 10 0 0 0 0 0 0 0 GICv3 226 Level eth0.common_irq
69: 5 0 0 0 0 0 0 0 GICv3 218 Level eth0.vm0
70: 0 0 0 0 0 0 0 0 GICv3 219 Level eth0.vm1
71: 0 0 0 0 0 0 0 0 GICv3 220 Level eth0.vm2
72: 0 0 0 0 0 0 0 0 GICv3 221 Level eth0.vm3
75: 0 0 0 0 3678 0 0 0 GICv3 416 Level eth1.common_irq
76: 1 0 0 0 0 0 0 0 GICv3 417 Level eth1.vm0
77: 0 0 0 0 0 0 0 0 GICv3 418 Level eth1.vm1
78: 2 0 0 0 0 0 0 0 GICv3 419 Level eth1.vm2
79: 0 0 0 0 0 0 0 0 GICv3 420 Level eth1.vm3
80: 0 0 0 0 0 0 0 0 GICv3 421 Level eth1.vm4
352: 4 0 0 0 0 0 0 0 gpio 125 Level 6810000.ethernet:00
root@lcfc-desktop:/home/lcfc#
flash.log (609.1 KB)
tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi (66.9 KB)
我们pinmux用的tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi

[ 0.8676 ] Pre-processing config: tegra234-mb1-bct-reset-p3701-0000.dts
[ 0.8719 ] Pre-processing config: tegra234-mb1-bct-device-p3701-0000.dts
[ 0.8767 ] Pre-processing config: tegra234-mb1-bct-cprod-p3701-0000.dts
[ 0.8815 ] Pre-processing config: tegra234-mb1-bct-gpioint-p3701-0000.dts
[ 0.8850 ] Pre-processing config: tegra234-mb1-bct-misc-p3701-0000.dts
[ 0.8916 ] Pre-processing config**: tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi**
[ 0.9057 ] Pre-processing config: tegra234-mb1-bct-padvoltage-p3701-0000-a04.dtsi
[ 0.9129 ] Pre-processing config: tegra234-mb1-bct-pmic-p3701-0000.dts
[ 0.9218 ] Pre-processing config: tegra234-mb1-bct-prod-p3701-0000.dts
[ 0.9308 ] Pre-processing config: tegra234-p3701-0000-sdram-l4t.dts
[ 2.1788 ] Pre-processing config: tegra234-mb1-bct-uphylane-si.dtsi
[ 2.1847 ] Pre-processing config: tegra234-mb1-bct-ratchet-p3701-0000.dts
[ 2.1885 ] Generating coldboot mb1-bct
[ 2.1891 ] tegrabct_v2 --chip 0x23 0 --mb1bct mb1_cold_boot_bct.cfg --misc t

WayneWWW · August 1, 2023, 6:36am

please share full dmesg as text file.

xianfei.chen · August 1, 2023, 6:46am

dmesg.log (87.4 KB)

WayneWWW · August 1, 2023, 6:49am

No error log is seen. Please review the hardware design too.

WayneWWW · August 1, 2023, 6:50am

I had a patch posted here.

Please check if everything is present.

xianfei.chen · August 1, 2023, 7:09am

dear WayneWWW
根据您的经验，HW需要检查那些问题？

WayneWWW · August 1, 2023, 7:13am

請問你現在所謂cannot link是在怎樣的環境？ port to port對接也失敗嗎？

xianfei.chen · August 1, 2023, 7:16am

port to port對接-------ethtool eth0 显示不能link. 然后显示也只有10M,而不是1g

WayneWWW · August 1, 2023, 7:17am

ethtool 的結果請分享一下

xianfei.chen · August 1, 2023, 7:31am

eth1是10g net，可以正常link；
eth0是1g net，不可以正常link；
我把对比图一起发给您

WayneWWW · August 1, 2023, 7:41am

你可以確認一下 /sys/kernel/debug/gpio 上面 phy reset那根pin有沒有被拉高嗎?

xianfei.chen · August 1, 2023, 7:46am

拉高了啊
root@lcfc-desktop:/home/lcfc# cat /sys/kernel/debug/gpio | grep phy
gpio-388 (PG.05 |phy_reset ) out hi
gpio-412 (PK.00 |switch-phy-int-input) in hi
gpio-413 (PK.01 |switch-phy-rst-high ) out hi
gpio-471 (PY.01 |phy_reset ) out hi
gpio-504 (PAG.00 |switch-phy-int-input) in hi
gpio-505 (PAG.01 |switch-phy-rst-high ) out hi
gpio-506 (PAG.02 |switch-phy-int-input) in hi
gpio-507 (PAG.03 |switch-phy-rst-high ) out hi
gpio-510 (PAG.06 |switch-phy-int-input) in hi
gpio-511 (PAG.07 |switch-phy-rst-high ) out hi
root@lcfc-desktop:/home/lcfc#

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ORIN RGMII can not LINK (phy 88e1512P)

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