Dear Nvidia Support Team,
I am currently working with the PCI interface, utilizing the Jetson AGX Xavier development kit as the root device and Xilinx’s AXI to PCI bridge IP as the endpoint. My goal is to establish communication between the root and endpoint, allowing data transfer in both directions.
At present, I have successfully enabled four PCIe bars and two AXI2PCI bars within the IP configuration. By running the “lspci -vvv” command on the development board, I can confirm that the bars are correctly initialized. Furthermore, I am able to read from and write to the endpoint memory.
However, I am encountering an issue when attempting to access the root memory from the endpoint. I have configured the root memory address within the AXI2PCI bar. Unfortunately, when I attempt to read or write to this AXI address, I am consistently receiving the value 0xFFFFFFFF, which is not the expected behavior.
It’s worth noting that the same endpoint has been successfully connected to an Intel kontron COMeboard, and I am able to read from and write to the memory on that board without any issues.
To help diagnose this issue, I have attached comparison logs for both the Nvidia and Intel configurations. The attached files are as follows:
Your assistance in resolving this matter is highly appreciated. If you could kindly review the attached files and provide guidance on how to address this issue, it would be of great help.
Thank you in advance for your support.