Data Read and Write from PCIE ENDpoint (FPGA) to Root Complex (Xavier Jetson) physical memory

Our Jetson Xavier board configured as RC and FPGA board acts as an EP. We write an application for a 64 or 32 bit physical address in memory. We are trying to initiate transactions from endpoint (FPGA) to root complex (Xavier Jetson). Whenever we initiate memory read transactions by transmitting a mem read TLP. We received a successful completion TLP on FPGA but the data present in TLP is 0xFFFFFFFF which is not the actual data present on that physical address when we devmem it on Xavier command window. Is there are any specific configuration setting we need to set for accessing physical memory of Xavier from external PCIE device or FPGA config as endpoint.

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There is no update from you for a period, assuming this is not an issue any more.
Hence we are closing this topic. If need further support, please open a new one.

Sorry for the late response, is this still an issue to support? Thanks