Communication Jetson Xavier with an FPGA board

Our Jetson Xavier board configured as RC and FPGA board acts as an EP which send data through memory write operation. But i’m observing the below errors,

testrp@testrp-desktop:~$ sudo busybox devmem 0x1f40000000 64 0x100e0000000
[ 631.837278] pcieport 0005:00:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0000(Receiver ID)
[ 631.837497] pcieport 0005:00:00.0: device [10de:1ad0] error status/mask=00040000/00400000
[ 631.837632] pcieport 0005:00:00.0: [18] Malformed TLP (First)
[ 631.837740] pcieport 0005:00:00.0: TLP Header: 40000018 00000500 00000000 00000001

Can you help us?

The FPGA endpoint in this case is not preparing the PCIe packets correctly. Please check the FPGA PCIe IP configuration correctly.
For example, from the ‘TLP Header’, it looks like it is 4DW in size… but decoding ‘40000018’ tells us that it should be a 3DW header.

@ShaneCCC The fourth DW is data. In pcie/aer/aerdrv_core.c TLP header is printed with first 4 DW irrespective of the header size.

From FPGA the packet is formed with address 0xe0000000 but I don’t know why 3rd DW contains all 0s. it should be 0xe0000000, right?

Byte enable field wasn’t set by FPGA. After Byte enable field properly set, now its working.

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