Jetson AGX Xavier, something wrong when testing CAN in normal mode( non-loopback )

[JohnSyu]

This is my first time using AGX Xavier, I have some questions about Jetson AGX Xavier.

I am trying to control a motor through Controller Areal Network (CAN) connections using the Nvidia Jetson Xavier Developer Kit. I made the following adjustments for canbus.

sudo busybox devmem 0x0c303000 32 0x0000C400
sudo busybox devmem 0x0c303008 32 0x0000C458
sudo busybox devmem 0x0c303010 32 0x0000C400
sudo busybox devmem 0x0c303018 32 0x0000C458
sudo modprobe can
sudo modprobe can_raw
sudo modprobe mttcan
sudo ip link set down can0
sudo ip link set down can1
sudo ip link set can0 type can bitrate 200000 loopback on
sudo ip link set can1 type can bitrate 200000 loopback on
sudo ip link set up can0
sudo ip link set up can1

I verified CAN connections using a loopback test and it works perfectly fine over CAN0 and CAN1: I am getting traffic using candump can0 in loopback mode. However there is no traffic in normal test mode.(sudo ip link set can0 type can bitrate 200000 sudo ip link set can1 type can bitrate 200000)

Besides, wiring is OK, and bitrate of two device matches, My Xavier is running JetPack 4.4.0

Someone had the same question as me, and the answer he got was enable PLLAON clock. Follow: “To use PLLAON as clock source” https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html#wwpID0E06B0HA
But I can’t find where “tegra194-a02-bpmp-p2888-a04.dtb” is. So, can anybody help me?

[beri.j90]

Hi,

I am having a similar issue with the Jetson Nano Nx linked here Jetson nano CAN via J17 pins only works with loopback on

[JerryChang]

@JohnSyu

But I can’t find where “tegra194-a02-bpmp-p2888-a04.dtb” is. So, can anybody help me?

hello syujen_1997,

assume you’d install JetPack release via https://developer.nvidia.com/nvidia-sdk-manager.
it’ll save the release image to your local host machine, the default path as ~/nvidia/nvidia_sdk/

and you shall find the binary file as below.
$OUT/Linux_for_Tegra/bootloader/t186ref/tegra194-a02-bpmp-p2888-a04.dtb
thanks

[JohnSyu]

I do use Nvidia SDK Manager to initialize AGX Xavier, but there is no ~/nvidia/nvidia_sdk

Does the hardware version lead to different results? Maybe my device is an earlier version？

[JerryChang]

@JohnSyu

but there is no ~/nvidia/nvidia_sdk

you should check on your local host for the release image.

[JohnSyu]

Can you describe it in more detail? How should I check it？

[JerryChang]

hello syujen_1997,

please see the “Target HW image folder” for the Step-2 of SDK Manager.

[JohnSyu]

hi, JerryChang

On my host, I can find “tegra194-a02-bpmp-p2888-a04.dtb” and path “~/nvidia/nvidia_sdk/”, but this is the new version of JetPack I just download tody. So, what I should do is to flash this new one to my AGX Xavier？

[JerryChang]

yes, please

[JohnSyu]

hi JerrtChang

I flash on my AGX Xavier again, and “flash of target hardware was skipped”, there is still no "~/nvidia/nvidia_sdk/"

on my Xavier

[JerryChang]

hello syujen_1997,

you should check your local host machine (i.e. x86 desktop) for the release image.

[JohnSyu]

Maybe I understand, please check it for me:

file tegra194-a02-bpmp-p2888-a04.dtb is under /home/johnsyu/nvidia/nvidia_sdk/JetPack_4.4_Linux_JETSON_AGX_XAVIER/Linux_for_Tegra/bootloader/

can make sure in its .dts file look like:
clock@can1 {
allow_fractional_divider = <0x1>;
allowed-parents = <0x121 0x5b 0x13a 0x5e>;
clk-id = <0x9>;
};

clock@can2 {
allow_fractional_divider = <0x1>;
allowed-parents = <0x121 0x5b 0x13a 0x5e>;
clk-id = <0xb>;
};

and tegra194-p2888-0001-p2822-0000.dtb is under /home/johnsyu/nvidia/nvidia_sdk/JetPack_4.4_Linux_JETSON_AGX_XAVIER/Linux_for_Tegra/kernel/dtb/ (Although there are three files with the same name “tegra194-p2888-0001-p2822-0000.dtb”)
can make sure in its .dts file look like:
clocks-init {
compatible = “nvidia,clocks-config”;
status = “okay”;
disable {
clocks = <0x4 0x9 0x4 0xb>;
};
};

mttcan@c310000 {
pll_source = “pllaon”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5e>;; /New entry/
clock-names = “can_core”, “can_host”, “can”, “pllaon”;
};
mttcan@c320000 {
pll_source = “pllaon”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5e>;; /New entry/
clock-names = “can_core”, “can_host”, “can”, “pllaon”;
};

when turn these two .dts back to .dtb, flash OS on AGX Xavier

should I do something else?

[JerryChang]

hello syujen_1997,

it looks correct, please overwrite the binary files under $OUT/Linux_for_Tegra/bootloader/ and re-flash your target.

[JohnSyu]

please, how can I overwrite the binary files under $OUT/Linux_for_Tegra/bootloader/

on web enable PLLAON it write “Convert the DTS file to DTB, or build the kernel DTB if you edited the source files.”

how can I build the kernel DTB?

[JerryChang]

cp commands.

[JohnSyu]

copy files: tegra194-a02-bpmp-p2888-a04.dtb and tegra194-p2888-0001-p2822-0000.dtb to $OUT/Linux_for_Tegra/bootloader/ ?

but the file tegra194-p2888-0001-p2822-0000.dtb is under $OUT/Linux_for_Tegra/kernel/dtb/, do I should overwrite this .dtb file in $OUT/Linux_for_Tegra/bootloader/ ?

[JerryChang]

hello syujen_1997,

don’t you disassembler the dtb file into text file for modification?
please overwrite the binary where it came from.

[JohnSyu]

oh! I got it, I’m trying to re-flash my Xavier to verify can-bus

[JohnSyu]

Now, I have finish flashing my Xavier, but under /sys/kernel/debug/bpmp/debug/clk/can1/parent, it shows “osc”, how can i choose pllaon as parent clock

[JerryChang]

hello syujen_1997,

by default, the PLLAON clock is disabled on T194 L4T platforms to conserve power.
please see developer guide, Configuring Clocks for the [To use PLLAON as clock source] session to enable PLLAON.
thanks