Updating the clock frequency in Device tree on jetson nx

Hi,
I have been trying to configure CAN-BUS on the JETSON NX development board with a CAN transceiver SN65HVD230.

My requirement is to to make a change on CAN clock rate in device tree. I am completely new in linux field and i want to make my CAN clock rate to 40MHZ. Can you provide any device tree related documents, tools which is used to update device tree. Also the procedure for decompiling the image and how to update the device tree and how to flash it again to the board.

Please explain the build and image creation procedure and how we can replace the dtb.

Thanks in advance.

Hi aravind:
Link to follow for kernel image update:

For Flashing device:

Now comes to CAN clock part:
If you want to set exact 40MHz:
Follow this:
To achieve 40MHz, first you need to set CAN parent clock as pllaon.
Please follow below doc to do so:
https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fclocks.html%23wwpID0E06B0HA

Check “ To use PLLAON as clock source” section

Also, by default, CAN clock rate requested is 50MHz from MTTCAN kernel driver. So to use 40MHz, make below change in driver:
The mttcan kernel driver sets the CAN clock rate. Follow the instructions in the Kernel Customization topic’s section Obtaining the Kernel Sources with Git to obtain kernel source code, then update the clock rate in the mttcan driver as in this code snippet:

.set_can_core_clk = true,

.can_core_clk_rate = 50000000, //// modify here (in Hz) so it should be 40000000

.can_clk_rate = 200000000, //// four times of core clk rate

Build the kernel and flash with the new kernel Image.
You can also directly copy mttcan.ko in the target under /lib/…

Let me know if you face any issues.

Thanks,
Shubhi

Hi,
I was following the procedure of kernal customization. But after building the kernel there is something related to signing the kernel and dtb files. Can u give detailed document for kenel signing procedure because am unable to find the script you mentioned in the procedure ( ./l4t_sign_image.sh ).

Thanks
Aravind.

I do not think signing is required. Just update kernel Image and flash device.

Hi,
I found a new jet pack 4.5 release. Has this update solves above mentioned clock rate issue?

Thanks and regards,
Aravind.

It’s not an issue. CAN clock is changed to save power. But if you want to change, above are the steps.

Hi,
When i buiding externel kernel modules its showing j]kernel configuration is invalid. Please go through the following command and errors.

command: make ARCH=arm64 –C /linux-headers-4.9.140-tegra-linux_x86_64 M=$(pwd)
ERROR: Kernel configuration is invalid.
include/generated/autoconf.h or include/config/auto.conf are missing.
Run ‘make oldconfig && make prepare’ on kernel src to fix it.

make: *** No rule to make target ‘–C’. Stop.

Thanks & regards

Hi,

While running the command for creative sd card image using customized kernel, its showing jetson-disk-image-creator.sh file/directory not found.

how i will get that .sh script. Any solution?

Thanks.

Hi,
Can you tell me which document and step you followed to create sd card image?

Hi,
I followed steps specified in Flashing to an SD Card in the NVIDIA Jetson Linux Developer Guide 32.5 Release.

Also i have one other doubt. Is it possible to build kernel image other than that given in the above document.

Thanks.

Hi Shubhi,
I found the following discussion and in that you are explaining the same problem of mine. For this issue is it required to build the whole image or simply we can edit the device tree as per your suggestion. Also please mention whether we need to do below procedure in the host system or Jetson system. Thank you

Regards,
Aravind.

Hi,
Thank you. I found the script. Now i can able to flash. But as i said earlier i have to edit the device tree and enable Pllaon because i want to make CAN to work in 40 Mhz speed . I am following the procedure provided in the developer guide.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html#wwpID0E06B0HA

But i have a doubt in editing of clocks-init section. I mentioned the part below:

Edit the kernel DTS file to make CAN use PLLAON as parent and remove PLLAON from list of clocks to be disabled:
clocks-init{
compatible = “nvidia,clocks-config”;
disable {
/* Edit clocks property to remove clock provider + clock id pair for PLLAON. */
};
};

Here what we need to put inside disable part. Thank you.

Regards,
Aravind.

Hi aravind,
Remove 0x5e from the disable section.
If it is like below:
clocks = <0x15f 0x5e 0x4 0x9 0x4 0xb>;
change it to:
clocks = <0x15f 0x4 0x9 0x4 0xb>;

Thanks shubhi.

In the mttcan0 section i made the following edit. But when i try to convert it back to dtb its showing below given error.

edit:

pll_source = “pllaon”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b>,<&bpmp_clks, TEGRA194_CLK_PLLAON>;
clock-names = “can_core”, “can_host”, “can”, “pllaon”;

error:
dtc -I dts -O dtb tegra194-p2888-0001-p2822-0000.dts > tegra194-p2888-0001-p2822-0000.dtb
Error: tegra194-p2888-0001-p2822-0000.dts:5297.66-67 syntax error
FATAL ERROR: Unable to parse input tree

Line which shows the error is ,

clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b>,<&bpmp_clks, TEGRA194_CLK_PLLAON>;

Thank you

Hi,
Can you tell me what were the contents in disable section before?

Hi,

Below given is the disable section now after removing 0x5e.

clocks-init {
compatible = “nvidia,clocks-config”;
status = “okay”;

	disable {
		clocks = <0x14d 0x4 0x9 0x4 0xb>;
	};
};

But this error is happening in MTTCAN section mentioned in the previous message,

Thank you

before edit:

clocks-init {
compatible = “nvidia,clocks-config”;
status = “okay”;

	disable {
		clocks = <0x14d 0x5e 0x4 0x9 0x4 0xb>;
	};
};

Ok thanks.
Can you edit mttcan0 like this:
pll_source = “pllaon”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5e>;
clock-names = “can_core”, “can_host”, “can”, “pllaon”;

Use as it is this content.

Ok Thank you. I will try that.

Regards,
Aravind