I could follow these steps (To use PLLAON as clock source with Updating the clock frequency in Device tree on jetson nx / Setup CAN with PLLAON as clock source) on my jetson Xavier (JetPack 4.5.1, NV Power Mode: MAXN), but if I check the pll_source, it is still osc.
If I open /sys/kernel/debug/bpmp/debug/dt on the jetson, I see allowed-parents = <0x121 0x5b 0x5e 0x13a>
On my host pc: tegra194-p2888-0001-p2822-0000.dtb
$ dtc -I dtb -O dts -f tegra194-p2888-0001-p2822-0000.dtb -o tegra194-p2888-0001-p2822-0000.dts
pll_source = “pllaon”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b 0x4 0x5e>
clock-names = “can_core”, “can_host”, “can”, “osc”, “pllaon”;clocks-init{
…
disable{
clocks = <0x4 0x9 0x4 0xb>;
};
};
$ dtc -I dts -O dtb -f tegra194-p2888-0001-p2822-0000.dts -o tegra194-p2888-0001-p2822-0000.dtb
Flash…Check on Jetson
$ xxd /proc/device-tree/mttcan@c310000/clocks
00000000: 0000 0004 0000 011c 0000 0004 0000 000a …
00000010: 0000 0004 0000 0009 0000 0004 0000 005b …[
$ sudo cat /sys/kernel/debug/bpmp/debug/clk/can1/parent
osv
$ sudo cat /proc/device-tree/mttcan@c310000/pll_source
osc
/sys/kernel/debug/bpmp/debug/clk/can1# cat possible_parents
clk_32k osc pll_aon pll_c
$ dtc -I fs /sys/firmware/devicetree/base | less
mttcan@c310000 {
compatible = “nvidia,tegra194-mttcan”;
clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5b>;
resets = <0x5 0x4>;
reg-names = “can-regs”, “glue-regs”, “msg-ram”;
clock-names = “can_core”, “can_host”, “can”, “osc”;
rx-config = <0x40 0x40 0x40>;
pll_source = “osc”;
mram-params = <0x0 0x10 0x10 0x20 0x0 0x0 0x10 0x10 0x10>;
status = “okay”;
interrupts = <0x0 0x28 0x4>;
phandle = <0x185>;
reg = <0x0 0xc310000 0x0 0x400 0x0 0xc311000 0x0 0x32 0x0 0xc312000 0x0 0x1000>;
reset-names = “can”;
linux,phandle = <0x185>;
tx-config = <0x0 0x10 0x0 0x40>;
};
clocks-init {
compatible = “nvidia,clocks-config”;
status = “okay”;disable {
clocks = <0x14d 0x5e 0x4 0x9 0x4 0xb>;
};
};
Thanks for any help!
