Setup CAN with PLLAON as clock source

Hi all,

with my Jetson Xavier AGX, I want to use CAN with PLLAON as clock source (i.e. was the default with earlier Jetpack versions).
I tried to follow the instructions in, section “To use PLLAON as clock source”. But I don’t manage to get it right; the clock (under /sys/kernel/debug/bpmp/debug/clk/can1/parent) still seems to be set to osc.

Here is what I did:

  • flash a default Jetpack 4.4.1 using the command line tool on the xavier

  • on my Linux host I use the dtc tool to decompile the tegra194-a02-bpmp-p2888-a04.dtb file and edit it such that the clocks section for the can devices looks like this:

    clock@can1 {
    allow_fractional_divider = <0x1>;
    allowed-parents = <0x121 0x5b 0x13a 0x5e>;
    clk-id = <0x9>;

    clock@can2 {
    allow_fractional_divider = <0x1>;
    allowed-parents = <0x121 0x5b 0x13a 0x5e>;
    clk-id = <0xb>;

    Then I convert it back to .dtb and store it at the same place as the original .dtb and flash it to the xavier with
    sudo ./ -r -k bpmp-fw-dtb jetson-xavier mmcblk0p1

  • Likewise, I edit the tegra194-p2888-0001-p2822-0000.dtb file to make the clocks-init section look like this:

     clocks-init {
       compatible = "nvidia,clocks-config";
       status = "okay";
       disable {
         clocks = <0x145 0x4>;

    and the mttcan section

    pll_source = “pllaon”;
    clocks = <0x4 0x11c 0x4 0xa 0x4 0x9 0x4 0x5e>;
    clock-names = “can_core”, “can_host”, “can”, “pllaon”;

then convert it to .dtb and store it under Linux_for_Tegra/kernel/dtb, then flash it with
sudo ./ -r -k kernel-dtb jetson-xavier mmcblk0p1

  • on the xavier, cat /sys/kernel/debug/bpmp/debug/clk/can1/parent still returns osc

  • checking the device tree on the xavier with dtc -I fs /sys/firmware/devicetree/base | less, I see my changes in the .dts file

  • However I notice in dmesg the following output:

    [ 18.216351] CAN device driver interface
    [ 18.242706] mttcan c310000.mttcan: unable to set CAN_CLK parent
    [ 18.260225] mttcan c310000.mttcan: probe failed
    [ 18.261622] mttcan c320000.mttcan: unable to set CAN_CLK parent
    [ 18.280971] mttcan c320000.mttcan: probe failed
    [ 18.313406] can: controller area network core (rev 20120528 abi 9)
    [ 18.313914] NET: Registered protocol family 29
    [ 18.321826] can: raw protocol (rev 20120528)

Does somebody know what I do wrong? Or how I could figure out what goes wrong?

Please follow below doc to do so:

Check “ To use PLLAON as clock source” section

Thank you. Yes, that is what I tried, but did not get it to work. I must have done something wrong with the BPMPFW dtb.

However I managed to get it to work by flashing the BPMPFW dtb from an earlier Jetpack release, and a modified kernel dtb as described in the documentation.

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Could you please describe the solution, which helped you to solve the problem. Thanks!

I simply pulled the tegra194-a02-bpmp-p2888-a04.dtb file from an earlier Jetpack release (I think it was 4.2, but am not sure) and flashed it alongside the changed tegra194-p2888-0001-p2822-0000.dtb (this one from the Jetpack 4.4.1 release, decompiled, modified, and recompiled as described in the documentation and my post above).

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