Jetson Thor T5000 Module - 10G Ethernet PHY Implementation Reference

Robotics & Edge Computing Jetson Systems Jetson Thor
,
1

Dear NVIDIA Team,

We are designing a custom carrier board that supports dual 10GBASE-T, 1G, 100Mbps, and PCIe interfaces from the Jetson Thor T5000 module.

For 10G design implementation, there is a high-level reference in the Jetson Thor Series Modules Design Guide. However, no schematic reference is available in the design files for the 10G PHY (AQR113-B0-C) implementation. Kindly provide the schematic reference.

We are planning to implement dual 10G Ethernet using the HS_UPHY1_L4 and HS_UPHY1_L5 lines with two 10G PHYs. Please confirm whether this configuration is supported on the Jetson Thor T5000 module, both at the hardware level and with the required software support.

Regarding 1G and 100Mbps Ethernet, I would like to understand how these interfaces can be implemented on the carrier board.

I see a reference in the design guidelines document using a PCIe controller (Ethernet over PCIe). However, the PHY used in the reference design is not available for procurement. I would like to know whether you can suggest an alternative PCIe-to-Ethernet PHY/controller and whether it is possible to use one PCIe controller for 1G Ethernet and the other for 100Mbps Ethernet.

Alternatively, please let us know whether the AQR113-B0-C 10G PHY can be connected to MGBE Controllers 2 and 3 and configured to support 1G and 100Mbps Ethernet.

Please confirm whether these configurations are supported by the hardware and default software, without requiring any additional software customization from our side, except for the pinmux configuration.

Regarding PCIe, we plan to connect a PCIe Gen4 x8 device to C4 and a PCIe Gen5 x2 device through an M.2 connector to C3.

Kindly confirm whether the above configurations are supported and provide the reference design files for the 10G PHY implementation at the earliest.

Regards,
Anoop

4

Hi,

Any update on my request.

Regards,
Anoop

6

Hi,

  1. 10G PHY (AQR113C) schematic reference: We do not have a Jetson Thor reference schematic for using AQR113C. However, you can refer to the AQR113C circuit in the Jetson AGX Orin Dev kit carrier board.

  2. Dual 10G Ethernet on HS_UPHY1_L4/L5: This configuration is supported at the hardware level.

  3. 1G / 100Mbps Ethernet: MGBE I/F can not operate at 1G or 100M. However, an external PHY may provide 1G/100M connectivity on the RJ45 side through rate adaption using Pause Frames.

    This configuration is outside our POR and has not been validated on Jetson Thor. Please confirm the PHY’s capability with its vendor and validate the configuration on your platform.

  4. PCIe Gen4 x8 (C4), PCIe Gen5 x2 (C3): This configuration is supported. However, C4 is unavailable when the MGBE interfaces are used because they share UPHY lance. Please refer to Table 7-3 in Design Guide.

Thank you,

7

Hi @hiwata ,

Thank you for your response.

I have a few follow-up queries regarding the 1G/100Mbps Ethernet implementation and would appreciate your clarification before we finalize the carrier board design.

1. Software Support for PCIe-Based Ethernet (1G/100Mbps):

I noticed that the Jetson Thor Series Modules Design Guide includes a reference for implementing 1G/100Mbps Ethernet using a PCIe controller through UPHY Lane 4, along with concept schematics showing the RTL8126-VB-CG Ethernet controller.

Does NVIDIA provide default BSP/kernel driver support for this PCIe-based Ethernet implementation, or is only the hardware reference provided? Would any additional driver integration or software customization be required?

2. Alternative PCIe-to-Ethernet Controller:

Since the RTL8126-VB-CG is currently unavailable for procurement, could you recommend any alternative PCIe-to-Ethernet controllers that are compatible with Jetson Thor? Also, please clarify whether the required drivers are already supported in the default Jetson Thor software.

3. 1G/100Mbps Ethernet Using MGBE C2/C3 with External PHY:

As per your previous response, we understand that the MGBE interface cannot directly operate at 1G or 100Mbps. However, an external PHY may provide 1G/100Mbps connectivity on the RJ45 side through rate adaptation using Pause Frames.

Based on this, we would like to explore connecting MGBE C2 and C3 to external AQR113-B0-C PHYs, with the MGBE-to-PHY host interface operating at the supported speed and the external PHY handling rate adaptation on the Ethernet side.

Could you please clarify whether this architecture is feasible with MGBE C2/C3? Also, does the default Jetson Thor BSP provide the necessary driver and software support for this implementation, or would additional software customization be required?

We understand that this configuration is outside NVIDIA’s POR scope and has not been validated on Jetson Thor. Nevertheless, we would appreciate any available guidance regarding MGBE interface compatibility and software requirements to help us assess the feasibility and finalize the hardware design.

4. Updated PCIe and 10GbE Mapping:

Based on the previous feedback, we have modified the interface mapping as follows:

Controller UPHY Lane Interface Mapping
C5 UPHY_[8:11] PCIe Gen4 x4 To PCIe Gen4 x4 Device
C3 UPHY_[6:7] PCIe Gen5 x2 M.2 PCIe connector
MGBE C0 UPHY_[12] 10GbE AQR113-B0-C PHY – 10GBASE-T
MGBE C1 UPHY_[13] 10GbE AQR113-B0-C PHY – 10GBASE-T

Please confirm whether this updated configuration is supported by the Jetson Thor T5000 module.

We would appreciate your clarification on the above points, so that we can finalize the interface implementation and close the pending queries.

Regards,
Anoop