Looking at the datasheet for the TX1 SOM it says under the Peripheral Interfaces that the SOM supports 3xUART however looking at the schematics for the developer carrier board it has 4xUART connections. Can you indeed use 4xUART with the TX1 SOM?
The are allocated by the following on the carrier board:
UART 0 - Debug UART header
UART 1 - Camera/GPIO Header
UART 2 - M.2/PCIe Header
UART 3 - BT/Header Option
The Tegra X1 chip has four UART controllers.
On the developer kit carrier board, one UART goes to J21, and is set up to work as a serial console. Another UART goes to the camera module, which has an access point at J17. I’m not sure how it is wired, but apparently another serial UART is associated with the M.2 connector. Bluetooth has a UART associated with it as well.
Note that in debug mode some UART functionality reverts to the debug header and may change other UART function, but this is not independent UART.
If you disable serial console, you could use J21 as a general purpose serial UART. Similar if you remove the camera module and configure without the camera (access at J17). I’m not sure what you would need to do to use the M.2 connector UART.
If you can use i2c or SPI, there are additional serial data devices. Do you specifically need a serial UART?
Looking at the dev board schematics there is a UART3 on pins H9/H10/G9/G10. This is also noted next to ut as UART4 (Tegra X1). I can find nothing in the datasheet that that shows support for this. Is this indeed a UART?
One thing which seems confusing to me is that apparently the carrier board (I’m looking at OrCAD) schematic lists “UART0” through “UART4”, while data sheet of the carrier board lists “UART0” through “UART3”. Thus the schematic has 5 UARTs…this disagrees with the Tegra X1 TRM.
The schematic “BOM rev A” is where UART4 was added, so this was not originally shown. I’m guessing that the data sheet was not updated at that time, but probably should have been if the revision were correct. However, this revision might have been a 1-off naming error where one information source started at UART0, but the other information source started at UART1, and UART4 was added accidentally when really it would need to translate between 0-based and 1-based numbering. This latter possibility is what I’d bet on, as the TRM lists UARTs in the form of “UART A” through “UART D” (no “UART E” in the TRM). In other words, the revision hit only one document, but should have hit two documents…but the revision turned out to be a mistake, and so references to UART4 (a fifth “ghost” UART) in reality are UART3 (or UART D). Confusing!
The schematic is not clear as to how UART4 is connected, as a group of pins (page 4) is marked both UART3 and UART4, but the actual BGA pins show UART1 and UART3 (UART4 is never shown as a concrete pin on that group of pins). I’d be very curious as to the exact nature of OrCAD revision A. Personally I think until clarification I’d consider “UART3”, “UART4”, and TRM “UART D” to be the same UART.
My question is whether it is UART3/UART4 is it ACTUALLY a UART. The datasheet only lists 3 available but there are 4 on the schematic.
The TRM says there are 4 UARTs, which should be correct. However, labels differ between TRM and schematic. I believe UART0 through UART3 are correct, and that the case of seeing UART4 probably needs to be translated to UART3. TRM-to-schematic translation A:D->0:3, with “4” being an error needing to be called “3”.
It’s not an error.
There are total four UARTs on TX1 module which are named as UART[4:1], while they are named as UART[3:0] on carrier board.
The mapping is:
UART1 (TX1) --> UART0
UART2 (TX1) --> UART2
UART3 (TX1) --> UART1
UART4 (TX1) --> UART3 (It’s used for WIFI/BT module)
e.g. The UART marked as “UART4 (Tegra X1)” on schematic Page4 actually means its name on TX1 module.
Found this while searching around - our application is going to need all four ports. Are all of them supported in the Linux BSP?
I would like to echo tcanham’s question; we need four ports as well. (This is declared in the JETSON TX1 DATASHEET DS-07224-010_v0.91 on page 9.)
Also, could I verify that what you posted in #7 above is correct? What you wrote disagrees with the TX1 datasheet, (pages 8 and 38), which calls UART2 as WIFI/BT module.
(BTW, doesn’t it seem a little ridiculous to have that kind of index mismatching? UART2->UART2, then UART3->UART1? This should be fixed up to avoid confusion.)
UART4 (TX1) --> UART3 (It’s used for WIFI/BT module) means UART4(TX1) is not routed out and occupied by internal WiFi/Bt of TX1 module. And so only 3 UARTs can be used. UART2 is used for external WiFi/Bt.
All above you can find in page 54 of OEM DG.
Page 56, Roger that. (For anyone reading this post, be sure you are distinguishing carefully between Tegra Chip, Jetson SOM, and Development Carrier Board,… at least with UART numbering almost nothing matches as you map between them).
I appreciate the reply, I hope you have a great day!
Thanks mcsauder for reminding me to get a new version, it is page 56 in latest version, mine is old, updated in May.
I want to use UART3 on J17 of TX1 as general purpose.
So Can anyone tell how to enable this ? and if already enable how to use this?
This is the output of dmesg | grep tty
root@tegra-ubuntu:/home/ubuntu# dmesg | grep tty
[ 0.000000] Kernel command line: fbcon=map:0 console=tty0 console=ttyS0,115200n8 androidboot.modem=none androidboot.serialno=P2180A00P00940c003fd androidboot.security=non-secure tegraid=188.8.131.52.0 ddr_die=2048M@2048M ddr_die=2048M@4096M section=256M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 debug_uartport=lsport,0 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff2bf000 nvdumper_reserved=0xff23f000 core_edp_mv=1125 core_edp_ma=4000 gpt android.kerneltype=normal androidboot.touch_vendor_id=0 androidboot.touch_panel_id=63 androidboot.touch_feature=0 androidboot.bootreason=pmc:software_reset,pmic:0x0 root=/dev/mmcblk0p1 rw rootwait
[ 0.000000] console [tty0] enabled
[ 5.774369] 70006000.serial: ttyS0 at MMIO 0x70006000 (irq = 68) is a Tegra
[ 5.781033] console [ttyS0] enabled, bootconsole disabled
[ 5.792248] 70006040.serial: ttyTHS1 at MMIO 0x70006040 (irq = 69) is a SERIAL_TEGRA
[ 5.801791] 70006200.serial: ttyTHS2 at MMIO 0x70006200 (irq = 78) is a SERIAL_TEGRA
[ 5.815603] 70006300.serial: ttyTHS3 at MMIO 0x70006300 (irq = 122) is a SERIAL_TEGRA
So i need to use ttyTHS1/2/3 right?
J17 corresponds to “/dev/ttyTHS2”.