This is actually a PCIe specification. The TX2 PCI controller supports either gen. 1 or gen. 2 speeds. If the end device can handle rev./gen. 2, then this will be used; if not, the signal will throttle back to rev./gen. 1 speeds. If the signal isn’t good enough for that, then there will be no use of the PCIe end device.
Gen./rev. 1 is 2.5GT/s with 8b/10b encoding. Gen./rev. 2 is 5GT/s with 8b/10b encoding. This means one lane at gen. 1 handles a theoretical max of 2GT/s applied to data, and a gen. 1 lane has a theoretical max of 4GT/s throughput for the data. A “gigatransfer/sec” is basically a bit per sec, so if gen. 1, then divide by 8 for bytes/sec, or 250MB/s for one lane; for gen. 2 one lane is 500MB/s theoretical max. See:
Whether or not you’ll actually achieve this depends on part if your components are truly gen. 2 compatible, and this includes signal quality. Failing to exactly match the board layout for PCIe might mean some gen. 2 devices clock back to gen. 1, or a gen. 1 might not even work.
If you need more bandwidth, then you will either need more lanes or hardware capable of later PCIe revisions, e.g., the Xavier. Note that although Xavier supports up to rev. 4 that this requires some very good engineering of traces to prevent falling back to a lower revision.