We are trying to get Jetson Nano into L1SS mode.
I have made the below changes
- Enabled CONFIG_PCIEASPM and CONFIG_PCIEASPM_POWERSAVE in file : /Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/configs/tegra_deconfig
- Removed “nvidia,disable-clock-request;” from file : /Linux_for_Tegra/sources/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pcie.dtsi
After building and flashing Image on Jetson Nano Board
I could still see “nvidia,disable-clock-request” under /proc/device-tree/pcie@1003000/pci@1,0
root@ifxhost:/proc/device-tree/pcie@1003000/pci@1,0# ls -al
total 0
drwxr-xr-x 2 root root 0 Jul 21 18:55 .
drwxr-xr-x 5 root root 0 Jul 21 18:55 …
-r–r–r-- 1 root root 4 Jul 21 18:56 ‘#address-cells’
-r–r–r-- 1 root root 20 Jul 21 18:56 assigned-addresses
-r–r–r-- 1 root root 4 Jul 21 18:56 device_type
-r–r–r-- 1 root root 4 Jul 21 18:56 name
-r–r–r-- 1 root root 4 Jul 21 18:56 nvidia,afi-ctl-offset
-r–r–r-- 1 root root 4 Jul 21 18:56 nvidia,disable-aspm-states
-r–r–r-- 1 root root 0 Jul 21 18:56 nvidia,disable-clock-request
-r–r–r-- 1 root root 4 Jul 21 18:56 nvidia,num-lanes
-r–r–r-- 1 root root 28 Jul 21 18:56 phy-names
-r–r–r-- 1 root root 16 Jul 21 18:56 phys
-r–r–r-- 1 root root 0 Jul 21 18:56 ranges
-r–r–r-- 1 root root 20 Jul 21 18:56 reg
-r–r–r-- 1 root root 4 Jul 21 18:56 ‘#size-cells’
-r–r–r-- 1 root root 5 Jul 21 18:56 status
lspci command output:
Capabilities: [240 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=8us PortTPowerOnTime=50us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
T_CommonMode=0us LTR1.2_Threshold=0ns
L1SubCtl2: T_PwrOn=50us
To cross check my changes on the Jetson Nano board
- Time stamp of dtb file(File: /boot/kernel_tegra210-p3448-0000-p3449-0000-b00.dtb) matches my build time.
- I have decompiled the dtb file(File: /boot/kernel_tegra210-p3448-0000-p3449-0000-b00.dtb) and generated the dts File.
- I did not see “nvidia,disable-clock-request” tag from the generated dts file.
Software Used: We are suing the 32.6.1 BSP Release Package.
Please let us know the changes required and process to get Jetson Nano into L1SS mode also process/command to know if the Nano configured to L1SS Mode properly
Kindle provide the update on this…
Hi,
By default the kernel dtb is loaded from specific partition but not the rootfs. So if what you did was just replacing a dtb file under /boot, then it won’t take effect.
Please put it to Linux_for_Tegra/kernel/dtb/ and flash with command
sudo ./flash.sh -r -k DTB _your_board_name mmcblk0p1. #please modify _your_board_name to match your board config.
It is working with the above command but we are using the below command to create image
jetson-disk-image-creator.sh -o sd-blob.img -b jetson-nano -r 300
Which internally will call the flash.sh script right ?? then it should have flashed the dtd partition also.
Please do let us know how to make dts changes get reflected using the jetson-disk-image-creator.sh script or i am missing anything here…
Hi,
After jetpack4.6/rel-32.6.1, the dtb is on the QSPI-nor flash of the module.
Thus, creating a sdcard image won’t really have effect for your DTB change.
if we have dtb changes then is this the only way to push the dtb changes on target ?? or there any ways like having secondary boot option ??
You can try to add FDT field inside your /boot/extlinux/extlinux.conf. This will make dtb read from rootfs.
yes with FDT option it is working.
I have one query when I sync the 32.6.1 source for NANO
l4t_sign_image.sh script is not synced but the flash.sh script still looks for the l4t_sign_image.sh for signing.
I could able to see l4t_sign_image.sh script file getting synced for Xavier.
Is signing not required for NANO or am missing something in sync operation ??
Kindle provide the update on this…
we are yet to get any response for my query??
reposting the query again.
4t_sign_image.sh script is not synced but the flash.sh script still looks for the l4t_sign_image.sh for signing.
I could able to see l4t_sign_image.sh script file getting synced for Xavier.
Is signing not required for NANO or am missing something in sync operation ??
If you can update the dtb, and it can get read successfully, then you don’t need to care about the sign.
This topic is just for updating PCIe related change in device tree and how to update device tree. If you have more questions regarding sign, you can file new topic.
Thanks for the clarification.
After the integrating FDT changes we are seeing the below issue:
lspci not getting detecting network card after a soft reboot
Recovery method:
Disable ASPM and then soft reboot
echo performance > /sys/module/pcie_aspm/parameters/policy (enter as sudo -s)
Reset pcie and then soft reboot
echo “1” > /sys/bus/pci/devices/0000:01:00.0/reset (entering as sudo -s)
please do let us know if you need more info for this issue to root cause the issue.
Are you talking about that disabling ASPM can make your network card work?
Do you have any dmesg to share after you enable ASPM and NIC not work?
soft_reboot.txt (43.1 KB)
Attached is the dmesg for NIC not detected by lspci…
Can you please provide update on this.
There is no update from you for a period, assuming this is not an issue any more.
Hence we are closing this topic. If need further support, please open a new one.
Thanks
Hi,
- Are you seeing reboot issue only if L1SS is enabled?
- If yes, change aspm to performance , reboot & verify.
- Also, don’t do pci reset before reboot.
echo “1” > /sys/bus/pci/devices/0000:01:00.0/reset → Don’t use this command.
- Does NIC works properly in the first boot with L1SS enabled?
- Instead of soft reboot, do cold reboot(shutdown completely & then power on) and share observations.
- Can you capture LA traces and see if training sets are exchanging between Tegra & NIC?