We are encountering two issues with our existing NVIDIA Orin Nano development board.
First, we intended to reconfigure the original PCIE C7 from an x2 lane to two separate x1 lanes (C7 and C9). After splitting the lanes, the system fails to boot when an NVMe drive is inserted into the original M.2 slot. Below is a breakdown of the modifications we have implemented.
Second, on our custom-designed carrier board, we modified the DP signals in the pinmux table to HDMI signals. However, there is no HDMI output after re-flashing the firmware.
Could you advise which critical steps we may have omitted for both of the above scenarios?
Let’s just focus one topic here. Please file another topic for your HDMI issue.
For PCIe C7+C9, please also check developer guide to modify ODMDATA before flash.
We have added the line ODMDATA=“gbe-uphy-config-9,hsstp-lane-map-3,hsio-uphy-config-0”; to the flashing configuration file Jetson-orin-nano-devkit.conf in accordance with the Developer Guide.
What is the NVMe in use here? Which PCIe controller is that?
Do you have full UART log to share?
We are still using the original NVMe SSD to mount the Ubuntu system, and the NVMe drive remains installed in the original x2-lane M.2 slot. The system boots straight into the UEFI Shell when debugging, and the full debug logs are provided below.
debug(1).txt (40.3 KB)
What is the purpose to do C7 to C7+C9 on the Orin Nano devkit? It sounds not quite meaningful.
So you break your M.2 key M slot itself when trying to splitting it into 2 controller?
On our custom carrier board, the original C7 lane has been split into C7 and C9. C7 remains connected to the NVMe SSD, while C9 is used for a USB hub chip. Therefore, we first need to successfully split C7 on the Orin Nano DevKit before conducting tests on our custom board.
I don’t see any reason to do this on NV devkit. Why not just do this on your custom board?
Actually, I think you already did it correctly. You enable two controllers at same time on a shared hardware of devkit.
The behavior becomes unstable which sounds expected.
NV devkit is not for this kind of test.
The hardware of the Orin Nano DevKit is 100% confirmed to be intact. Therefore, if our software configuration can successfully split the lane into two x1 channels on the Orin Nano DevKit and boot into the system via the NVMe SSD without issues, it will verify that our software configuration is correct, facilitating subsequent hardware debugging on our custom carrier board.
Currently, the NVMe SSD cannot be detected on our custom carrier board either.
Below is the schematic diagram for splitting the x2 lane into two x1 lanes.
The method to split C7 x2 to C7 x1+ C9 x1 have been verified by many other end users and partners before.
Better review your hardware if device is not detected. Our developer guide also has the debug tips for missing PCIe device detection.
