PCIe Debug

[ggrutzeck]

Hi all,

we have a custom carrier board with a PCIe connection to a FPGA. It is a PCIe 3.0 link with 8 lanes on the C5 PCIe controller. But unfortunately we can not bring the link up. The FPGA is stuck in the Polling.Active of the LTSSM. What are the possible steps from the Jetson side to debug such a problem? In the TRM I found a register (0xd0), which has the current state of the LTSSM in it. But the encoding of this bitfield is not given in the TRM. Is it possible, that you share this encoding with us?

Edit: We could verify that both, the FPGA and the Jetson, are sending symbols at 2.5GT/s. Unfortunately we can not decode the symbols to check them with the PCIe specs.

What are the consequences of using nvidia,update_fc_fixup; in the device tree, when the link is not running at full speed and full width?

Best,
Gerrit

[ggrutzeck]

After looking into the data, which is seen by the FPGA. We noticed, that the Jetson module is sending the PCIe compliance pattern for 8b/10b.
What could be the reason for this? Is there some entry in the device tree, which could lead to such a behavior? Or some levels on some pins of the module?
Is it possible to readout via register, if the PCIe complex of the Jetson module is sending out the compliance pattern?

[kayccc]

Sorry for the late response, have you managed to get issue resolved or still need the support? Thanks

[ggrutzeck]

The issue is still open. It would be very helpful to readout the current state of the LTSSM.

[WayneWWW]

please check this page.

https://docs.nvidia.com/jetson/archives/r35.3.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=pcie#debug-pcie-link-up-failure

->Dump PCIE_RP_APPL_DEBUG_0 register, refer to TRM for register address of each controller. Accessing the controller’s address, which is not enabled, will cause a CBB power down error. When you share this information in NVIDIA developer forum, it will help us determine the LTSSM state.

[WayneWWW]

I found a register (0xd0), which has the current state of the LTSSM in it. But the encoding of this bitfield is not given in the TRM. Is it possible, that you share this encoding with us?

I am not sure about the “encoding” means here. Could you clarify? Are you saying the detail info of this register?

[WayneWWW]

Hi,

The result from 0xd0 offset bit[8:3] LTSSM state encoding is as follows.

* `define S_DETECT_QUIET 6'h00
`define S_DETECT_ACT 6'h01
`define S_POLL_ACTIVE 6'h02
`define S_POLL_COMPLIANCE 6'h03
`define S_POLL_CONFIG 6'h04
`define S_PRE_DETECT_QUIET 6'h05
`define S_DETECT_WAIT 6'h06
`define S_CFG_LINKWD_START 6'h07
`define S_CFG_LINKWD_ACEPT 6'h08
`define S_CFG_LANENUM_WAIT 6'h09
`define S_CFG_LANENUM_ACEPT 6'h0A
`define S_CFG_COMPLETE 6'h0B
`define S_CFG_IDLE 6'h0C
`define S_RCVRY_LOCK 6'h0D
`define S_RCVRY_SPEED 6'h0E
`define S_RCVRY_RCVRCFG 6'h0F
`define S_RCVRY_IDLE 6'h10
`define S_RCVRY_EQ0 6'h20
`define S_RCVRY_EQ1 6'h21
`define S_RCVRY_EQ2 6'h22
`define S_RCVRY_EQ3 6'h23
`define S_L0 6'h11
`define S_L0S 6'h12
`define S_L123_SEND_EIDLE 6'h13
`define S_L1_IDLE 6'h14
`define S_L2_IDLE 6'h15
`define S_L2_WAKE 6'h16
`define S_DISABLED_ENTRY 6'h17
`define S_DISABLED_IDLE 6'h18
`define S_DISABLED 6'h19
`define S_LPBK_ENTRY 6'h1A
`define S_LPBK_ACTIVE 6'h1B
`define S_LPBK_EXIT 6'h1C
`define S_LPBK_EXIT_TIMEOUT 6'h1D
`define S_HOT_RESET_ENTRY 6'h1E
`define S_HOT_RESET 6'h1F

[ggrutzeck]

Thank you very much, that is very helpful.