we config Xavier module as EP mode followed in use PCIe endpoint mode to communication in two Xaviers.
and connect xavier to a x86 server. but failed to estalish link, x86 cannot recognize it, and the dmesg shows xavier failure as following:
tegra-pcie-dw 141a0000.pcie_ep: UPHY init failed for PCIe EP:-116
What does that mean? why link estalish failed?
Thank you.
Hi,
When PERST# is deasserted by x86, PCIE_RECLK should be provided to Jetson AGX PCIe slot. If a valid PCIE_CLK is not available then we will see the error mentioned above. Please check why x86 is not providing valid REFCLK when PERST# is deasserted.
Thanks,
Manikanta
Sorry, correct one information, the server is ARM64 arch.
And EP init done at now.
But still can not see xavier pcie device on server.
Could you help figure out why?
Thank you very much.
Does it mean link training done when log “EP init done” shows up?
How to confirm link training done on Xavier EP mode?
We config pcie5 controller address at 0x141a0000 as EP mode.
How to check registers related to link status?
Thank you very much.
Hi,
Are you saying that PCIe link is not up and not able to find Jetson AGX in host machine lspci output?
Read the following registers.
0x141a00d0 #This will tell LTSSM state, reading this ~10 times
0x141a00cc #BIT(0) is link status
Thanks,
Manikanta
Read back data as following. Is there any related register description manual?
root@nv-desktop:/home/nv# ./busybox-armv8l devmem 0x141a00d0
0x00002018
root@nv-desktop:/home/nv# ./busybox-armv8l devmem 0x141a00cc
0x00000002
Thank you very much.
PCIe LTSSM state is in compliance mode. Please check the setup .
Register definition can be found in TRM, check PCIE_RP_APPL_DEBUG_0.
LTSSM states are not defined here, however SMLH_LTSSM_STATE=0x3 corresponds to compliance mode.
I’m confused, as the TRM shows that 0xd0 and 0xcc register names prefixed with PCIE_RP, which is used for Root Port, right?
But I’m tuning it as EP mode. Is it still to check these registers?
Thank you very much.
IP is same for EP & RP. DM_TYPE register bit will decide in which mode PCIe operating. So, yes these registers are correct for EP.
Thanks,
Manikanta
Could you help give some clues?
I really have no idea why PCIe C5 EP mode not work.
Thank you very much.
Hi,
Double check if instructions in mentioned in the document are followed correctly.
https://developer.nvidia.com/embedded/dlc/jetson-agx-xavier-series-pcie-endpoint-design-guidelines-application-note
PCIe connector between x86 & Jetson AGX and the boot sequence should be followed correctly to bring up the AGX in Endpoint mode.
Thanks,
Manikanta
I check synopsys-DWC_pcie_reference.pdf, but cannot find for LTSSM current state explanation.
what does ‘compliance mode’ mean here?
Thank you very much.
Could you help figure out how to config EP using PCIe Gen 3.0?
what registers are involved?
Thank you very much.
This is Nvidia specific APP logic, so it won’t be available in DWC document.
Compliance mode is used to generate traffic on Rx and Tx lanes and measure signal integrity. One way to send PCIe link to compliance mode is by terminating Rx lanes with 50 ohm.
Make following change in hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-pcie.dtsi,
nvidia,max-speed = <4>; → nvidia,max-speed = <3>; in pcie_ep@141a0000 DT node.
I don’t see any where this property getting override by some other dtsi file. If you face any problems you can directly hard code max_speed in driver kernel/nvidia/drivers/pci/dwc/pcie-tegra.c
Thanks,
Manikanta
OK, I’ll try first to set max-speed to Gen 3.
And, how to debug linking up process?
For now, I need to know what stage is ltssm current state, such as detect/polling/config/L0, or anything else.
Thank you very much.
Reviewed comliance mode as you replied before, it means RC and EP sending compliance test parttern to each other?
Thank you very much.
Hi,
Are you able to get the link up in Gen3?
Thanks,
Manikanta