How to use ep mode of NX pcie controller(use PCIe x4 lane0)

I’ve been trying to use NX devkit as PCIe endpoint mode,I follow the AGX procedure to modify,details as follows:

  1. In the extracted Jetson Linux release directory, edit p3668.conf.common Set bit 12 of the ODMDATA value, i.e. change it from 0xB8190000 to 0xB8191000
  2. Run this command to reflash the device: sudo ./ jetson-xavier-nx-devkit mmcblk0p1
    But when I finished updating, there was an error in startup, as follows:
    TICE: BL31: v2.5(release):ef8af0b99
    NOTICE: BL31: Built : 20:57:59, May 16 2022
    pmp: init
    bpmp: tag is 128431eec76692047e1ac1ebc0392266
    sku_dt_init: not sku 0x00
    TC: Nk_early initialized
    -seil_early initialized
    se initialized
    hwwdt initialized
    e94_ec_get_ec_list: found 45 ecs
    ernal DT initialized
    vmon_setup_monitors: found 3 monitors
    vmon initialized
    uc initialized
    n_populate_monitors: found 73 monitors

on initialized
mc initialized
reset initialized
nvhs initialized
uphy_early initialized
emc_early initialized
392 clocks registered
clk initialized
io_dpd initialized
thermal initialized
thermal_mrq initialized
i2c initialized
vrmon_dt_init: vrmon node not found
vrmon_chk_boot_state: found 0 rail monitors
vrmon initialized
regulator initialized
avfs_clk_platform initialized
soctherm initialized
aotag initialized
powergate initialized
TC: OP-TEE version: 6f444acf (gcc version 9.3.0 (Buildroot 2020.08)) #2 Tue May 17 04:00:18 UTC 2022 s initialized
pend initialized
64_late initialized
mrq_init initialized
strap initialized
TC: c initialized
emc_mrq initialized
imary CPU initializing
k_dt initialized
tj_init initialized
uphy_dt initialized
uphy_mrq initialized
uphy initialized
ec_swd_poll_start: 281 reg polling start w period 47 ms
ec_late initialized
hwwdt_late initialized
reset_mrq initialized
ec_mrq initialized
fmon_mrq initialized
clk_mrq initialized
avfs_mrq initialized
mail_mrq initialized
i2c_mrq initialized
tag_mrq initialized
console_mrq initialized
mrq initialized
clk_sync_fmon_post initialized
clk_dt_late initialized
noc_late initialized
pm_post initialized
dbells initialized
dmce initialized
cvc initialized
avfs_clk_mach_post initialized
avfs_clk_platform_post initialized
cvc_late initialized
regulator_post initialized
rm initialized
console_late initialized
clk_dt_post initialized
mc_reg initialized
pg_post initialized
profile initialized
fuse_late initialized
extras_post initialized
bpmp: init complete
entering main console loop
] TC: Primary CPU switching to normal world boot
etson UEFI firmware (version r34.1-975eef6 built on 2022-05-16T20:58:45-07:00)

ROR: MPIDR 0x80000000: exception reason=0 syndrome=0xbe000000
ERROR: **************************************
ERROR: RAS Error in L2, ERRSELR_EL1=0x200:
ERROR: Status = 0xfc006612
ERROR: IERR = SCF to L2 Slave Error Read: 0x66
ERROR: SERR = Error response from slave: 0x12
ERROR: Overflow (there may be more errors) - Uncorrectable
ERROR: Uncorrectable (this is fatal)
ERROR: MISC0 = 0x80000000400000
ERROR: MISC1 = 0x20240000000
ERROR: ADDR = 0x8000000003eb00c0
ERROR: **************************************

Is there a step I’m missing and what do I need to do?

Please refer to Xavier NX cannot be detected as EP mode - #6 by Manikanta

I did it with reference to the steps of AGX, but the program will crash after flashing;
Step and error print as above;

AGX modify p2972-0000.conf.common file, but for NX, I modify p3668.conf.common file, is this correct?

Do I have to modify the value of “odmdata” for ep to take effect? I haven’t changed this value to make ep take effect now,But not sure if there is a problem;


Rel-34 not yet supported PCIe EP due to some bug. Please fallback to rel-32 if you want to try this function.

What could this bug cause?Is there any problem description?

Is the use of rel-32 also modify “odmdata” to enable ep mode?

You can check the document first.

What could this bug cause?Is there any problem description?

The bug just means PCIe EP mode cannot work.

After I flashed the machine with version 32.6.1, I completed the configuration on the desktop, but after the configuration was completed, the device stayed on the desktop and could not be operated. When I restarted the power, it made me reconfigure it again. The same is true for version 32.7.2

I used version 32 and changed pcie to ep mode, but the following error was reported during the startup process, what is the reason for this?
[ 0.739436] iommu: Adding device 141a0000.pcie_ep to group 0
[ 0.740107] iommu: Adding device 14160000.pcie to group 1
[ 6.453279] tegra-pcie-dw 141a0000.pcie_ep: Setting init speed to max speed
[ 6.471274] tegra-pcie-dw 141a0000.pcie_ep: Failed to get 3V slot regulator: -19
[ 6.478577] tegra-pcie-dw 141a0000.pcie_ep: Failed to get 12V slot regulator: -19
[ 6.487350] tegra-pcie-dw 141a0000.pcie_ep: zjb finish initialize endpoint