Public SCF PMU event semantics on Jetson AGX Orin

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

Hi,

I am trying to use the documented public SCF PMU events on Jetson AGX Orin as the main memory-related signal for CPU-driven workloads.

From the public TRM, I understand that CPU memory reads/writes go through:
CPU cluster → ACI → SCF → SNOC → MCF

My question is specifically about the public SCF PMU events such as:

  • scf_pmu/bus_access_rd/
  • scf_pmu/bus_access_wr/
  • scf_pmu/scf_cache_refill/
  • scf_pmu/scf_cache_wb/

Could NVIDIA clarify, at a high level, what boundary these events correspond to?

In particular:

  1. Do bus_access_rd / bus_access_wr count accesses entering SCF from the CPU/cluster side, or traffic leaving SCF toward SNOC / memory-controller side?
  2. Do these events include accesses that are satisfied by the SCF system cache (L4), or only accesses that miss in SCF and continue toward memory?
  3. Are MMIO or other non-DRAM paths excluded from these events?

Even a brief clarification of the intended counting boundary would be very helpful.

Thank you.

4

Hi,
Publicly we have tegrastats showing loading of CPU cores:
Tegrastats Utility — NVIDIA Jetson Linux Developer Guide

Seems like you need further information about CPU processing tasks. Is there a reason to get the operations in detail?

5

Hi, thanks.

Yes, there is a reason for asking at this level of detail.

This is part of my Bachelor’s thesis, where I am studying memory-bandwidth measurement for CPU-driven workloads on Jetson AGX Orin. I am not trying to monitor CPU processing load in general. My goal is to use the public SCF PMU events as the main memory-related signal, and for that I need to understand what boundary they represent at a high level.

For example, I am trying to understand whether these public events are closer to:

  • traffic entering SCF from the CPU / cluster side
  • traffic leaving SCF toward SNOC / MCF / DRAM
  • or accesses internal to SCF, including requests satisfied by the SCF system cache

tegrastats is useful for system monitoring, but it does not answer that semantic question. I am specifically asking about the intended counting boundary of the documented public SCF PMU events:

  • scf_pmu/bus_access_rd/
  • scf_pmu/bus_access_wr/
  • scf_pmu/scf_cache_refill/
  • scf_pmu/scf_cache_wb/

Even a high-level clarification such as “CPU-side of SCF”, “memory-side of SCF”, or “includes accesses satisfied by SCF cache” would already be very helpful for my thesis.

Thank you.