PWM very noisy and unstable on Jetson Nano Developer Kit

Robotics & Edge Computing Jetson Systems Jetson Nano
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1

Hi there,
I have a Jetson Nano Developer Kit 4GB (B01 I think, the one with two camera headers) and I am trying to get a controllable PWM output. I configured the 40-pin header using /opt/nvidia/jetson-io/jetson-io.py and enabled both pwm0 and pwm2, but after rebooting and trying to get it working by manually changing values using sysfs, it does not seem to work no matter what I do. What happens is that as soon as I enable the channel, I get a very noisy output on pin 32 (or 33, no matter which PWM channel I try), with sometimes a piece of signal that does look like the PWM signal I configured. When I disable it, the signal is gone. Here’s what the signal looks like:

DSO_ScreenCap
DSO_ScreenCap800×480 13.5 KB

This is how I’m configuring the PWM channel:

cd /sys/class/pwm/pwmchip0
echo 0 > export
cd pwm0
echo 20000 > period
echo 10000 > duty_cycle
echo 1 > enable

/sys/kernel/debug/pwm shows:

platform/70110000.pwm, 1 PWM device
 pwm-0 (pwm-regulator): requested enabled period: 2500 ns duty: 0 ns polarity: normal 

platform/7000a000.pwm, 4 PWM devices
 pwm-0 (sysfs): requested enabled period: 20000 ns duty: 10000 ns polarity: normal
 pwm-1 (pwm-regulator): requested enabled period: 8000 ns duty: 1440 ns polarity: normal
 pwm-2 ((null)): period: 0 ns duty: 0 ns polarity: normal
 pwm-3 (pwm-fan): requested enabled period: 45334 ns duty: 0 ns polarity: normal

I would have liked to post a screenshot of my jetson-io config but as a new user I can’t. Anyway, as far as I’m concerned it’s fine, has pwm0 on pin 32 and pwm2 on pin 33.

At first I thought the device tree overlay was not considered, but it seems that the bootloader is picking it up. Here’s the boot log:

U-Boot 2020.04-g6b630d64fd (Jul 09 2021 - 08:53:46 -0700)

SoC: tegra210
Model: NVIDIA Jetson Nano Developer Kit
Board: NVIDIA P3450-0000
DRAM:  4 GiB
MMC:   sdhci@700b0000: 1, sdhci@700b0600: 0
Loading Environment from SPI Flash... SF: Detected mx25u3235f with page size 256 Bytes, erase size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  2 1 0 
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1...
Found /boot/extlinux/extlinux.conf
Retrieving file: /boot/extlinux/extlinux.conf
1147 bytes read in 33 ms (33.2 KiB/s)
L4T boot options
1:	primary kernel
2:	Custom 40-pin Header Config
Enter choice: 2:	Custom 40-pin Header Config
Retrieving file: /boot/initrd
7159329 bytes read in 345 ms (19.8 MiB/s)
Retrieving file: /boot/Image
34338824 bytes read in 1502 ms (21.8 MiB/s)
append: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 console=ttyS0,115200n8 debug_uartport=lsport,4 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff780000 core_edp_mv=1075 core_edp_ma=4000 gpt tegra_fbmem=0x800000@0x92ca9000 is_hdmi_initialised=1  earlycon=uart8250,mmio32,0x70006000  root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 quiet root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0
Retrieving file: /boot/kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb
244415 bytes read in 32 ms (7.3 MiB/s)
## Flattened Device Tree blob at 83000000
   Booting using the fdt blob at 0x83000000
ERROR: reserving fdt memory region failed (addr=0 size=0)
ERROR: reserving fdt memory region failed (addr=0 size=0)
   Using Device Tree in place at 0000000083000000, end 000000008303eabe
copying carveout for /host1x@50000000/dc@54200000...
copying carveout for /host1x@50000000/dc@54240000...
DT property /chosen/nvidia,bluetooth-mac missing in source; can't copy
DT property /chosen/nvidia,wifi-mac missing in source; can't copy
DT property /psci/nvidia,system-lp0-disable missing in source; can't copy

Starting kernel ...

I’ve been looking everywhere and I just can’t figure out what is happening. If anyone could help, that’d be awesome!
Cheers!

5

hello montoyo2,

here’s max/min rate the PWM, which calculated from the clock source.
could you please check possible clock parents of pwmN, i.e. $ cat /sys/kernel/debug/bpmp/debug/clk/pwm8/possible_parents
please review current rate of pwmN (in Hz), $ cat /sys/kernel/debug/bpmp/debug/clk/pwmN/rate
for example,
clock source, pllp_out0 which has a rate of 102 MHz.
hence,
Max Rate = 102Mhz/ 256 = 398437 Hz = 2510 ns
Min Rate = 102Mhz/ (256* 2^13) (i.e. 13-bits Frequency divider (bits 0:12)) = 48.63Hz = 20561324 ns

6

Hi Jerry,
Thank you for your reply. Just one note: I have re-installed the OS, thinking that updating to the latest version would help. Unfortunately, that didn’t change anything.

Anyway, I couldn’t cat /sys/kernel/debug/bpmp/debug/clk/pwm8/possible_parents because /sys/kernel/debug/bpmp doesn’t exist on my system. The only thing named bpmp I have found in /sys is /sys/firmware/devicetree/bpmp and when cat-ing /sys/firmware/devicetree/bpmp/status it says “disabled”.

I have also tried different values for the period and ended up with the same result :(

7

After poking around a bit I realized that this is not just a PWM issue, this applies to absolutely all GPIO pins. Googling around, I found that

The Jetson Nano carrier board uses TXB0108 bidirectional voltage-level translators on the GPIOs to go from the module’s 1.8 V levels to the headers 3.3 V levels. The data sheet for the TXB0108 states “With regard to capacitive loads, TXB translators are designed to drive up to 70 pF without issue.” The capacitance of my test leads is above 70 pF, so I tried an oscilloscope with 10 MΩ, 16 pF probes and the Jetson Nano outputs work fine.
(see Jetson Nano GPIO example problem - #13 by PinballWizard).

And indeed, switching to 10X attenuation on the probe did the trick…
Thanks anyway!