My question is regarding HDMI HPD (Hot Plug Detect), which is implemented via GPIO. How can this be modified?
Our board connects the HPD signal to GPIO 74 (J2 connector).
I would like to confirm whether the file tegra234-dcb-p3701-0000-a02-p3737-0000-a01_hdmi.dtsi uses GPIO 74 for HPD, and if not, how to generate a proper DCB file for this configuration.
I have checked Linux_for_Tegra/tools/dcb_tool/dcb_tool and would like to understand how to create a DCB for HDMI properly.
Basically the patches in this post are all the things you need for a rel-35 HDMI enable.
The user’s problem there was a wrong hardware. All the software patches he/she applied are correct.
A brief explanation: You need below items
The correct pinmux setting for the HPD pin. It is the fixed hardware pin GPIO Pin M.0 on the carrier board. You could not use any other GPIO to replace it.
The DCB image with HDMI mode. It will change the mode from DP to HDMI
Add the "os_gpio_hotplug_a " with the HPD GPIO in (1) in the kernel device tree and then do full flash.
You have to run full flash so that those changes will take effect to the DCE.
From this, I understand that GPIO (M, 0) should be configured.
According to page 11 of the Adaptation and Bring-up for Jetson AGX Orin document, GPIO (M, 0) corresponds to Port M, Pin Offset 0, which would be GPIO 76.
However, according to the Orin Pinmux table (Orin_Jetson_Series_Pinmux_Config_Template_2.0.xlsm), the relevant signal is:
K50 DP2_HPD DP_AUX_CH0_HPD GP74_HPD0_N 50k z DP_AUX_CH0_HPD Input
Based on this, I believe the HPD signal uses GPIO 74, which would correspond to Port L, Pin Offset 2.
Question 1: Why is there a difference between GPIO (M, 0) and the expected GPIO 74 from the Pinmux table?
Question 2: Is this HPD GPIO input configured through the DCB (Display Control Block), or is it entirely handled via the DTS (Device Tree Source) configuration shown above?
Question 3: According to the HDMI specification, HPD is active high. But from the signal name GP74_HPD0_N, it appears to be active low. From the Orin SoC’s perspective, is HPD active high or active low?
Is this HPD GPIO input configured through the DCB (Display Control Block), or is it entirely handled via the DTS (Device Tree Source) configuration shown above?
Both side needs this info.
Question 3: According to the HDMI specification, HPD is active high. But from the signal name GP74_HPD0_N, it appears to be active low. From the Orin SoC’s perspective, is HPD active high or active low?
Actually the detection is based on rising /falling edge and also the EDID, so whether active high or low does not matter.
I don’t understand how the K50 pin corresponds to Port M, pin 0 from the Pinmux table document (Orin_Jetson_Series_Pinmux_Config_Template_2.0.xlsm).
It seems to indicate GPIO3_PM.00 as Port M, pin 0, but where exactly is this string in the document? I can’t find it.
At what kind of document do you want to know here? The pinmux spreadsheet itself already told you it is GPIO3_PM.00. That PM.00 just indicates it is pin M,0.
You need to let the excel show you all the column in the same row and you will see that.
Those name like “GP74_HPD0_N” never means it is “GPIO74”. It is just a pin name inside of the SOM.