HDMI Output Issue on Custom Carrier Board for Jetson AGX Orin (DP to Micro HDMI conversion)

Hello,

We are developing based on the Jetson AGX Orin platform. The SOM is the same as the Development Kit, but we have developed a custom carrier board.

By default, the Development Kit uses DisplayPort output, but we are trying to switch the output to Micro HDMI on our custom board.

We referred to the following NVIDIA forum thread:

  1. PinMux Configuration
    Modified the following file:
    /Linux_for_Tegra/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi

The relevant pin configuration snippet:

dp_aux_ch0_hpd_pm0 {
nvidia,pins = “dp_aux_ch0_hpd_pm0”;
nvidia,function = “rsvd1”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
Although we considered setting the function to “hdmi”, we referred to the Orin_Jetson_Series_Pinmux_Config_Template_2.0.xlsm document, which only defines “DP” for this pin, so we used “rsvd1”.

According to the schematic, the HPD (Hot Plug Detect) signal is active high per HDMI specification, but the signal is inverted to active low by a BJT before entering the SoC. Therefore, TEGRA_PIN_PULL_NONE was used.

1.2 GPIO Modification
Unsure exactly what changes are required, but modified:
/Linux_for_Tegra/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi

Added TEGRA234_MAIN_GPIO(M, 0) for HPD.

  1. DCB Configuration
    Used the official NVIDIA-provided file:
    tegra234-dcb-p3701-0000-a02-p3737-0000-a01_hdmi.dtsi

The file contains a dcb-image definition.

Added HPD config as follows:

// for HDMI, 2025-06-23, HPD (Hot Plug Detect) Low Active
display@13800000 {
compatible = “nvidia,tegra234-hdmi”;
nvidia,display-type = “hdmi”;
status = “okay”;
os_gpio_hotplug_a = <&gpio TEGRA234_MAIN_GPIO(M, 0) GPIO_ACTIVE_LOW>;
};
3. DTS Extracted from dtb (tegra234-p3737-0000+p3701-0008-nv.dtb)
display@13800000 {
compatible = “nvidia,tegra234-hdmi”;
power-domains = <0x03 0x03>;
nvidia,num-dpaux-instance = <0x01>;
reg-names = “nvdisplay\0dpaux0\0hdacodec\0mipical”;
reg = <0x00 0x13800000 0x00 0xeffff 0x00 0x155c0000 0x00 0xffff 0x00 0x242c000 0x00 0x1000 0x00 0x3990000 0x00 0x10000>;
interrupt-names = “nvdisplay\0dpaux0\0hdacodec”;
interrupts = <0x00 0x1a0 0x04 0x00 0x1a3 0x04 0x00 0x3d 0x04>;
nvidia,bpmp = <0x03>;
clocks = <0x03 0x54 …>;
clock-names = “nvdisplayhub_clk\0nvdisplay_disp_clk\0nvdisplay_p0_clk\0nvdisplay_p1_clk\0dpaux0_clk\0fuse_clk\0dsipll_vco_clk\0dsipll_clkoutpn_clk\0dsipll_clkouta_clk\0sppll0_vco_clk\0sppll0_clkoutpn_clk\0sppll0_clkouta_clk\0sppll0_clkoutb_clk\0sppll0_div10_clk\0sppll0_div25_clk\0sppll0_div27_clk\0sppll1_vco_clk\0sppll1_clkoutpn_clk\0sppll1_div27_clk\0vpll0_ref_clk\0vpll0_clk\0vpll1_clk\0nvdisplay_p0_ref_clk\0rg0_clk\0rg1_clk\0disppll_clk\0disphubpll_clk\0dsi_lp_clk\0dsi_core_clk\0dsi_pixel_clk\0pre_sor0_clk\0pre_sor1_clk\0dp_link_ref_clk\0sor_linka_input_clk\0sor_linka_afifo_clk\0sor_linka_afifo_m_clk\0rg0_m_clk\0rg1_m_clk\0sor0_m_clk\0sor1_m_clk\0pllhub_clk\0sor0_clk\0sor1_clk\0sor_pad_input_clk\0pre_sf0_clk\0sf0_clk\0sf1_clk\0dsi_pad_input_clk\0pre_sor0_ref_clk\0pre_sor1_ref_clk\0sor0_ref_pll_clk\0sor1_ref_pll_clk\0sor0_ref_clk\0sor1_ref_clk\0osc_clk\0dsc_clk\0maud_clk\0aza_2xbit_clk\0aza_bit_clk\0mipi_cal_clk\0uart_fst_mipi_cal_clk\0sor0_div_clk”;
resets = <0x03 0x10 0x03 0x08 0x03 0x03 0x03 0x25>;
reset-names = “nvdisplay_reset\0dpaux0_reset\0dsi_core_reset\0mipi_cal_reset”;
hdcp_enabled;
status = “okay”;
memory-region = <0x20b>;
nvidia,disp-sw-soc-chip-id = <0x2350>;
interconnects = <0x58 0x92 0x59 0x58 0xa1 0x59>;
interconnect-names = “dma-mem\0read-1”;
iommus = <0x113 0x01>;
non-coherent;
nvidia,dcb-image = [55 aa …];
nvidia,display-type = “hdmi”;
os_gpio_hotplug_a = <0xf1 0x60 0x01>;
phandle = <0x20c>;

	nvdisplay-niso {
		compatible = "nvidia,tegra234-display-niso";
		iommus = <0x04 0x07>;
		dma-coherent;
	};
  1. Current Issue
    We are not sure if our custom board has boot issues.

When connecting the monitor via Micro HDMI, no display output appears.

According to NVIDIA documentation, only the DCB image and HPD settings should be needed, but it seems not working in our case.

Question
What could be wrong or missing in our configuration? Is there anything else to consider beyond DCB and HPD settings to get HDMI output working on a custom carrier board for Jetson AGX Orin?

Thank you for any help or suggestions.

*** Please note that this reply is generated by LLM automatically ***

Based on the provided context, I’ll offer a comprehensive analysis of the issue and provide suggestions for resolving the problem.

Summary of the Issue:

The developer is trying to switch the output from DisplayPort to Micro HDMI on a custom carrier board for the Jetson AGX Orin platform. They have applied the necessary software patches, including the correct pinmux setting for the HPD pin, DCB image with HDMI mode, and added the “os_gpio_hotplug_a” configuration. However, they are not getting any display output when connecting the monitor via Micro HDMI.

Analysis:

  1. Pinmux Configuration: The developer has modified the pinmux setting for the HPD pin to “rsvd1” instead of “hdmi” as suggested by the Orin_Jetson_Series_Pinmux_Config_Template_2.0.xlsm document. This might be a potential issue, as the HPD signal is active high per HDMI specification, but the signal is inverted to active low by a BJT before entering the SoC. It’s essential to verify that the pinmux configuration is correct and matches the hardware design.
  2. GPIO Modification: The developer has added TEGRA234_MAIN_GPIO(M, 0) for HPD, but it’s unclear if this is the correct GPIO configuration. It’s crucial to ensure that the GPIO configuration matches the hardware design and the pinmux setting.
  3. DCB Configuration: The developer has used the official NVIDIA-provided file tegra234-dcb-p3701-0000-a02-p3737-0000-a01_hdmi.dtsi, which contains a dcb-image definition. However, it’s essential to verify that the DCB image is correctly configured for HDMI output.
  4. DTS Extracted from dtb: The HDMI display node includes relevant clocks, resets, interconnects, and the dcb-image binary. The HPD GPIO is assigned as <0xf1 0x60 0x01>. It’s crucial to ensure that the DTS file is correctly configured and matches the hardware design.

Suggestions:

  1. Verify Pinmux Configuration: Double-check the pinmux configuration to ensure it matches the hardware design. Consider using the “hdmi” function instead of “rsvd1” for the HPD pin.
  2. Verify GPIO Configuration: Ensure that the GPIO configuration matches the hardware design and the pinmux setting. Verify that the TEGRA234_MAIN_GPIO(M, 0) configuration is correct.
  3. Verify DCB Configuration: Verify that the DCB image is correctly configured for HDMI output. Ensure that the dcb-image definition matches the hardware design.
  4. Verify DTS Configuration: Verify that the DTS file is correctly configured and matches the hardware design. Ensure that the HDMI display node includes all necessary clocks, resets, interconnects, and the dcb-image binary.
  5. Check Hardware Design: Verify that the custom carrier board’s hardware design matches the pinmux, GPIO, and DCB configurations. Ensure that the HPD signal is correctly connected and inverted to active low by a BJT before entering the SoC.
  6. Consult NVIDIA Documentation: Consult the NVIDIA documentation for Jetson AGX Orin to ensure that all necessary configurations are correct and up-to-date.
  7. Test and Debug: Test the configuration and debug any issues that arise. Use tools like the NVIDIA Jetson AGX Orin developer kit’s debug console to troubleshoot any problems.

Comparison with Similar Issues:

The issue is similar to the “CAN Message from Jetson Orin Nano not detected” issue, where the developer had to verify the pinmux configuration, GPIO configuration, and DCB configuration to resolve the problem. Similarly, in this case, verifying the pinmux, GPIO, and DCB configurations, as well as the DTS file, is crucial to resolving the issue.

In conclusion, the developer should verify the pinmux, GPIO, and DCB configurations, as well as the DTS file, to ensure that they match the hardware design. Additionally, consulting the NVIDIA documentation and testing and debugging the configuration can help resolve the issue.

Are you using Jetpack5 or Jetapck6?

I am using Jetpack 6, R36.4.3.
I would appreciate it if you could review my HDMI settings and let me know what I might be doing wrong.

The direction of your change is correct. Your method would work in Jetapck5 but won’t fully work on jp6.

Please refer to p3509-a02-p3767-0000.conf in your BSP directory. This config covers the 4 items for HDMI.

31 PINMUX_CONFIG=“tegra234-mb1-bct-pinmux-p3767-hdmi-a03.dtsi”;
32 PMC_CONFIG=“tegra234-mb1-bct-padvoltage-p3767-hdmi-a03.dtsi”;
33 OVERLAY_DTB_FILE+=“,tegra234-dcb-p3767-0000-hdmi.dtbo”;
34 DCE_OVERLAY_DTB_FILE=“tegra234-dcb-p3767-0000-hdmi.dtbo”;

After checking the UART log, the system stops at the following point.
Where should I look to enable HDMI monitor output?

I/TC: Primary CPU switching to normal world boot
UG: /dvs/git/dirty/git-master_linux/display/dce/init/dce-init.c
185 dce_dt_init failed, rc = 0x4000003c
UEFI firmware (version 36.4.3-gcid-38968081 built on 2025-01-08T01:18:20+00:00)
Abort: reason:0x301 Err:0x0 [(NULL)]
ERROR: camera-ip/isp5/isp5.c:2031 [isp5_pm_init] “ERROR: Failed to turn isp1 power on”
BUG: core/init/init.c:86 [init_all] “*** FIRMWARE INIT FAILED AT LEVEL 95 ***”

Maybe you should clarify what things did you do…

I applied the p3509-a02-p3767-0000.conf file.
Before building, I executed the following.

In .bashrc:

  • source /path/p3509-a02-p3767-0000.conf
  • so the following commands get executed:

====================following==================================

source "${LDK_DIR}/p3768-0000-p3767-0000-a0.conf"

PINMUX_CONFIG="tegra234-mb1-bct-pinmux-p3767-hdmi-a03.dtsi"
PMC_CONFIG="tegra234-mb1-bct-padvoltage-p3767-hdmi-a03.dtsi"
OVERLAY_DTB_FILE+=",tegra234-dcb-p3767-0000-hdmi.dtbo"
DCE_OVERLAY_DTB_FILE="tegra234-dcb-p3767-0000-hdmi.dtbo"

=============================================================

However, there is still no output on the Micro HDMI monitor. The UART log is as follows.


Why does the following error occur?

/dvs/git/dirty/git-master_linux/display/dce/init/dce-init.c:185  dce_dt_init failed, rc = 0x4000003c

I searched for this source code but could not find anything like it.

Please help me resolve this issue.


Partial UART log excerpt:

I> Successfully register DCE FW load task with MB2 loader

I> dce : oem authentication of header done
I> strt_pg_num(38672) num_of_pgs(1) read_buf(0xe2e1403d8)
I> strt_pg_num(38672) num_of_pgs(8) read_buf(0xe2e1403d8)
I> dce : meta-blob integrity check is success.
I> strt_pg_num(38680) num_of_pgs(512) read_buf(0xe2e0003c0)
I> strt_pg_num(39192) num_of_pgs(512) read_buf(0xe2e0403c0)
I> dce : will be decompressed at 0xe36000000
I> version 1 Bin 1 BCheckSum 0 content_size 0 Content ChkSum 1 reserved_00 0
I> Reserved10 0 BlockMaxSize 5 Reserved11 0
I> strt_pg_num(39704) num_of_pgs(512) read_buf(0xe2e0803c0)
I> dce : decompressed to 12068528 bytes
I> dce: plain binary integrity check is success
I> Partition name: A_adsp-fw
I> Size of partition: 2097152
I> Binary@ device:3/0 block-58240 (partition size: 0x200000), name: A_adsp-fw
I> strt_pg_num(58240) num_of_pgs(16) read_buf(0x40067a30)
I> strt_pg_num(58256) num_of_pgs(800) read_buf(0xe38800000)
I> dce: Authentication Finalize Done


DCE_R5_Init
MPU enabled
DCE_SW_Init


?UG: /dvs/git/dirty/git-master_linux/display/dce/init/dce-init.c:185 dce_dt_init failed, rc = 0x4000003c"


[ 11.182414] dce: dce_handle_irq_status:230 DCE ucode abort occurred


---

### Notes:

* The source file path (`/dvs/git/dirty/git-master_linux/display/dce/init/dce-init.c`) is not found in public repositories because it is an internal NVIDIA firmware source path embedded in debug messages.
* The error `dce_dt_init failed, rc = 0x4000003c` usually means the DCE firmware failed to initialize the display device tree node, often due to missing or incorrect device tree configuration or board data mismatch.

---

Please let me know if you want me to help analyze this further or suggest steps to resolve it.
[log_SOM3_20250704_1054.txt|attachment](upload://1q5wUTrtVKvZtv1LMXTnqq02OH2.txt) (83.7 KB)

Hi,

You cannot directly apply the same things to Orin AGX. p3767 files are for Orin NX/Orin Nano.

What I mean here is you should apply similar items to Orin AGX.

I understand that the configuration files like p3767 are for Orin NX and Orin Nano, and that Orin AGX requires different settings.

However, I do not have the expertise or resources to create a completely new pinmux and device tree configuration from scratch for Orin AGX.

Could NVIDIA provide:

  • Reference or example configuration files specifically for Jetson AGX Orin HDMI output?
  • Guidelines or documentation to help create or adapt these configurations?
  • Any tools or official support for generating the correct device tree overlays and pinmux settings for AGX Orin?

This would greatly help developers like me who need HDMI functionality but cannot develop these low-level configurations independently.

Even if the build completes successfully, the fusing options can still differ and cause issues.
Without knowing the correct fusing configuration, problems like boot failure or HDMI output issues may persist despite a successful build.

Therefore, clear documentation or examples of fusing and flashing options are essential for proper device initialization and troubleshooting.

Thank you for your understanding and support.

31 PINMUX_CONFIG=“tegra234-mb1-bct-pinmux-p3767-hdmi-a03.dtsi”;
32 PMC_CONFIG=“tegra234-mb1-bct-padvoltage-p3767-hdmi-a03.dtsi”;

You already did things correctly for a rel-35 version.

Just modify above two pinmux back to default one and then modify the dp_aux_ch0_hpd_pm0 setting just as you did in your first comment.

Just to clarify. All the things you did in this comment:

They are correct.

But for rel-36, you need to apply DCB setting to OVERLAY_DTB_FILE and DCE_OVERLAY_DTB_FILE field. And if you don’t want to create a new file, then you could use tegra234-dcb-p3767-0000-hdmi.dtbo. That file only has dcb setting. So even using it to Orin AGX is fine.

But you definitaly cannot use 3767 pinmux to a Orin AGX. So please just update dp_aux_ch0_hpd_pm0 pinmux in your Orin AGX pinmux and then assign this pinmux file.

You said:
“Just modify the above two pinmux files back to the default ones, and then modify the dp_aux_ch0_hpd_pm0 setting just as you did in your first comment.”

The settings for Orin Nx/Nano and AGX are as follows:
// Orin AGX
PINMUX_CONFIG=“tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi”;
PMC_CONFIG=“tegra234-mb1-bct-padvoltage-p3701-0000-a04.dtsi”;

// Orin Nx/Nano
PINMUX_CONFIG=“tegra234-mb1-bct-pinmux-p3767-hdmi-a03.dtsi”;
PMC_CONFIG=“tegra234-mb1-bct-padvoltage-p3767-hdmi-a03.dtsi”;

Where exactly should I revert to “default”?
While modifying dp_aux_ch0_hpd_pm0 is straightforward, how can I find the default values for PINMUX_CONFIG and PMC_CONFIG?
I cannot use the Orin Nx/Nano settings, and I have already applied the Orin AGX settings but it still doesn’t work. What should I do?

As I mentioned before, I modified and applied dp_aux_ch0_hpd_pm0 in the following files, but HDMI output did not appear:
PINMUX_CONFIG=“tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi”;
PMC_CONFIG=“tegra234-mb1-bct-padvoltage-p3701-0000-a04.dtsi”;

I believe many customers would like to switch from DisplayPort to HDMI.
Would it be possible to modify and distribute the configuration files accordingly?
Even if I try to study and handle it myself, the related documentation is quite confusing. Meanwhile, the products are sold at high prices, which is very frustrating.

I missed your last reply, so I am currently applying it.
I am using the following file:
jetson-agx-orin-devkit-industrial.conf
Therefore, I added the following lines to that file:

==========================================================
OVERLAY_DTB_FILE+=“,tegra234-dcb-p3767-0000-hdmi.dtbo”
DCE_OVERLAY_DTB_FILE=“tegra234-dcb-p3767-0000-hdmi.dtbo”

I would like to share my experience of enabling HDMI output on Jetson AGX Orin (custom carrier board), as it might help others struggling with similar issues.

📝 Environment
Platform: Jetson AGX Orin

L4T Version: R36.4.3

Board: Custom carrier board (SOM compatible with DevKit)

⚡ Final modifications that enabled HDMI output
1️⃣ Removed potential camera-related conflict
Error observed in log:

camera-ip/isp5/isp5.c:2031 [isp5_pm_init] “ERROR: Failed to turn isp1 power on”
Investigation:

sudo find ./Linux_for_Tegra/ -name isp5.c
./Linux_for_Tegra/source/nvidia-oot/drivers/video/tegra/host/isp/isp5.c
➡ Interestingly, there is no isp5_pm_init function in that source file.
I am raising this question to NVIDIA: Why is there a log referencing a function that does not exist in the source?

Solution applied:
Edited jetson-agx-orin-devkit-industrial.conf
➡ Removed unnecessary camera overlay DTBOs from OVERLAY_DTB_FILE:

tegra234-p3737-camera-dual-imx274-overlay.dtbo
tegra234-p3737-camera-e3331-overlay.dtbo
tegra234-p3737-camera-e3333-overlay.dtbo
tegra234-p3737-camera-imx185-overlay.dtbo
Reason: No camera on our board, but these overlays were generating errors.(i am not sure this is the main reason. cuz i made two modifcation. the other is dts modification about HDMI below)

2️⃣ Removed manual DTS HDMI configuration
Original DTS snippet I added:

// for HDMI, 2025-06-23, HPD(Hot Plug Detect) Low Active
display@13800000 {
compatible = “nvidia,tegra234-hdmi”;
nvidia,display-type = “hdmi”;
status = “okay”;
os_gpio_hotplug_a = <&gpio TEGRA234_MAIN_GPIO(M, 0) GPIO_ACTIVE_LOW>;
};

Action: I deleted this section.

Reason:
I applied NVIDIA’s official HDMI DTBO:

DCE_OVERLAY_DTB_FILE=“tegra234-dcb-p3767-0000-hdmi.dtbo”
To avoid potential conflicts, I decided to rely solely on NVIDIA’s DTBO.
(Note: I haven’t fully verified if this manual DTS conflicts directly with the DTBO — testing the HDMI output with the DTS intact would be useful for confirmation.)

✅ Result
➡ HDMI output worked after these changes.
Log_20250703_1317.txt (126.9 KB)

The attached file contains the log from a previous failure when HDMI output did not work.
Unfortunately, I wasn’t able to capture the log immediately after today’s failure.
However, the symptoms and log content from today’s failure are identical to the log from the failure on 2025-07-03 which is the failure i have confronted first.

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