Hi,
From reviewing the schematic, I can see that DC_IN_MONITOR is a 1:10 divided signal of the DC input, which is supplied when the CCG8 is powered on. I also noticed that this signal is provided exclusively to the CCG8D on GPIO P1.0.
However, next to the GPIO name, there is an “SNN” label. Normally, this indicates that a signal is not used. Could you confirm if this means the signal is unused in this specific design? If it is being used, what is its intended purpose?
I am checking this with the design team.
Thank you for clarifying. However a follow up question arises.
Looking into the CCG8 datasheet, the GPIO DC input voltage HIGH threshold is defined as 0.7 × VDD, where VDD corresponds to your VDDD_3V3_CCG at 3.3V, resulting in a threshold of 2.31V. Taking the 1:10 voltage divider into account, with the resistor values of 20kΩ and 200kΩ forming the divider network, the DC_IN voltage would need to be at least 2.31V × (200 + 20) / 20 = 25.41V (equivalent to 11 × 2.31V) for the GPIO to register a logical HIGH. However, according to the Jetson Thor documentation, the Micro-Fit input supports a voltage range of 9V to 28V, which means that for most of the time, the GPIO would only see a voltage level well below the 2.31V HIGH threshold, so a detection of DC presence would not work reliably across the full input voltage range when interpreted as a simple boolean input.
But, looking at the maximum allowable voltage on the GPIO, defined as the minimum of 6V or VDDIO + 0.5V, with VDDIO also being 3.3V, the maximum permissible GPIO voltage comes out to 3.8V. Working backwards through the divider, this corresponds to a maximum DC_IN of approximately 41.8V, which is well within the 28V upper limit, but does not resolve the issue at the lower voltage end.
Given this analysis, is it correct to conclude that DC_IN_MONITOR is not being used as a boolean digital input but rather as an analog signal to measure or estimate the actual DC input voltage level rather than simply detecting its presence? If so, could you elaborate on how the CCG8 processes this signal internally?
Regarding my specific design requirement of supporting DC input voltages up to 60V, would it be feasible to adjust the voltage divider ratio, for example from 20k:200k to something like 36k:620k, so that the scaled signal at the GPIO remains within the safe operating voltage range across the full extended input voltage range?
From the board designer: It’s an ADC pin on CCG8 and when it’s below 6.5V, the power path won’t be enabled.
