Rescan or hot-plug for FPGA-based PCIe EP device

Hi!

Consider a system with an FPGA-based PCIe device as endpoint, and the Jetson AGX Orin as root complex. I’m facing an issue, and it rises a flag about the final implementation:
a) I need to reboot the Jetson after progamming FPGA, because the device wasn’t enumerated/found, and it isn’t shown in lspci.
b) Considering an FPGA boot from flash, would be possible the Jetson to be ready before the FPGA boot.

I found some topics about other Jetsons, but nothing about the Agx Orin. Then, here are my questions:

  1. Is it possible to implement a hot-plug pcie device in Jetson Agx Orin?
  2. Can I execute a rescan without rebooting? I tried the “echo 1 > /sys/bus/pci/rescan”, but without success.

I’m using a Jetson Agx Orin DevKit, but maybe it will be migrated to industrial module. The tegra release is R32, revision 2.1.

The tegra release version you are using is a totally mistake. I think you may double check it again first.

I’m sorry, I was talking about Linux for Tegra version:
R35 (release), REVISION: 2.1,.

There is a method to let driver bind and rebind which could enumerate the device. Is it okay for you?

Yes, thanks Wayne! The driver unbind and bind solved my issue, for now.

Hi,

If you are designing a custom base board, then it means some adaptation configurations are needed.
Otherwise, your board may not work fine.

For Orin AGX series, you could refer to below document
https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=universal%20serial%20bus#jetson-agx-orin-platform-adaptation-and-bring-up
(please be aware that above link is for rel-36.3/jetpack6.0)

This document includes below configuration

  1. pinmux change & GPIO configuration
  2. EEPROM change as most custom boards do not have an EEPROM on it.
  3. Kernel porting
  4. PCIe configuration
  5. USB configuration
  6. MGBE configuration
  7. RGMII configuration

Thanks!

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