RGMII porting on Jp6.2

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
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1

Hi,

Jetpack version : 6.2
Board : custom designed
RGMII : KSZ9893RNXI-TR

I’m porting ksz9893 on our custom designed board for phy using with jetpack 6.2

I have check NV document and other topic on the forum

But it didn’t show any message in Dmesg,(such as ethernet@2310000)

I’ve ever porting another IC(ksz9031) on another custom designed board with Jp5.1.2

And it works fine, but it can’t work on Jp6.2 too

Here’s the dts for Jp512 with RGMII success

		/*EQOS*/
		ethernet@2310000 {
			compatible="nvidia,nveqos";
			status = "okay";
			nvidia,mac-addr-idx = <0>;
			nvidia,max-platform-mtu = <16383>;
			nvidia,pause_frames = <0>;
			phy-mode="rgmii-id";
			phy-handle = <&rgmii_phy>;
			/delete-node/ fixed-link;
			fixed-link{
					speed = <1000>;
					full-duplex;
			};

			mdio {
				compatible = "nvidia,eqos-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				rgmii_phy: phy@7{
					compatible= "ethernet-phy-ieee802.3-c22", "ethernet-phy-id0022.1620", "micrel,ksz9031";
					reg = <7>;
					device_type = "ethernet-phy"; 
					nvidia,phy-rst-pdelay-msec = <224>; 
					nvidia,phy-rst-duration-usec = <10000>; 
					interrupt-parent = <&gpio>; 
					interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
					micrel,reg-init = <0x3 0x12 0x7fff 0x880>;
					micrel,copper-mode;
					phandle = <0x21>;
					//max-speed = <1000>;
				};
			};
		};

Could you help to give me some suggestions for porting ksz9893 on Jp6.2 ?

3

But it didn’t show any message in Dmesg,(such as ethernet@2310000)

I guess you didn’t modify correct location in the device tree.

Check your full dts converted back from dtb and it will tell.

4

Yes, you’re right

The dts converted back from dtb show disabled

But I have check the ethernet@2310000 did not be used on other dts

Is there any place to modify it’s status?

5

any place could be fine if the final dtb would set it to enabled… I never memorize which file could be used to modify because that is meaningless thing if you know how device tree works…

6

Thanks for help

I’ve enabled it by setting at the final dts

And here’s the error message

nvethernet 2310000. ethernet: Adding to tommu group 52
nvethernet 2310000. ethernet: failed to read skip mac reset flag, default o
nvethernet 2310000. ethernet: failed to read MDIO address
nvethernet 2310000. ethernet: setting to default DA bit mask
nvethernet 2310000. ethernet: failed to get phy reset gio error: -2
nvethernet 2310000. ethernet: Ethernet MAC address: 00:11:14:1a: 6b:7d
nvethernet 2310000. ethernet: Macsec not enabled
nvethernet 2310000. ethernet: Macsec: Reduced MTU: 1466 Max: 16383
nvethernet 2310000. ethernet: eth1 (HW ver: 53) created with 8 DMA channels
nvethernet 2310000. ethernet eth1: Link is Up - 1Gbps/Full - flow control off

I can see interface eth1 in ifconfig, but I can’t ping 8.8.8.8 successfully
it shows connect: Network is unreachable

Here’s my dts now, according to log, reset ping may have some problem, but it seems not really matter

Could you give me some suggestions?

            ethernet@2310000 {
                status = "okay";
                nvidia,mac-addr-idx = <1>;
                // nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
                nvidia,phy-reset-gpios = <&pca6408_20 6 GPIO_ACTIVE_LOW>; //control by i2c-gpio
                phy-mode = "rgmii-id";
                /* 1:10G, 0:5G */
                nvidia,uphy-gbe-mode = <1>;
                /* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
                nvidia,phy-iface-mode = <0>;
                nvidia,max-platform-mtu = <16383>;
                nvidia,pause_frames = <0>;
                // phy-handle = <&phy>; //no need for switch
                /delete-node/ fixed-link;
                fixed-link {
                    speed = <1000>;
                    full-duplex;
                };

                mdio {
                    compatible = "nvidia,eqos-mdio";
                    #address-cells = <1>;
                    #size-cells = <0>;

                    switch@1 {
                        // status = "okay";
                        compatible = "microchip,ksz9477";
                        reg = <1>;
                        // phy-mode = "rgmii";
                        nvidia,phy-rst-pdelay-msec = <224>; /* msec */
                        nvidia,phy-rst-duration-usec = <10000>; /* usec */
                    };
                    switch@2 {
                        // status = "okay";
                        compatible = "microchip,ksz9477";
                        reg = <2>;
                        // phy-mode = "rgmii";
                        nvidia,phy-rst-pdelay-msec = <224>; /* msec */
                        nvidia,phy-rst-duration-usec = <10000>; /* usec */
                    };
                };
            };
7

What is this setting doing here? This is not a UPHY.

8

Actually I’m not really sure about that

I’m not familiar with RGMII, so have some reference by document and forum

I add it according to the document

11

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