SD Card Read/Write speed is too slow

Hi all,

I’m testing Jetson Nano with my custom carrier board and sd card Read/Write is too slow. Read speed is 1.5MB.
And I’m using 512GB samsung sd card and it supports uhs speed.

Actually I found ‘9875882.diff’ patch for this issue and applied it. But it’s not getting better.
When I check dmesg logs, setting signal voltage as 180 has no problem.
But I could see below error log after setting send cid function.
‘fallback to HS enumeration’

Here is my mmc1/ios info.

clock: 50000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don’t care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 2 (sd high-speed)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)

Could you help me about this issue?

Thanks in advance.

dmesg.txt (55.6 KB)

Here is my dmesg txt.

Thakns,
Dongjin Ha.

Hi,

Please search the forum topic first.

This is duplicated with Slow SD card access speed (read+write) with Jetson Nano production module

Thanks.

Hi @WayneWWW,

I already checked that case and applied patch#11.

sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;

I could see these property from my dtb at sdmmc3. But my sdcard speed is still ‘high speed’ mode.

[ 1.477846] mmc1: new high speed SDXC card at address 0001

Should I need to add another modification?

Thanks,
Dongjin Ha.

Hi,

Why do you mention patch#11? I don’t see any patch in #11 on that topic.

The patch is to remove clk limit in dts.

max-clk-limit = <400000>;

I already remove clk limit in my dts.
Here is my SDMMC3 properties in my common.dtsi.

sdhci@700b0400 {
status = “okay”;
/delete-property/ keep-power-in-suspend;
/delete-property/ non-removable;
cd-gpios = <&gpio TEGRA_GPIO(Z, 2) 0>;
nvidia,cd-wakeup-capable;
nvidia,vmmc-always-on;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
mmc-ddr-1_8v;
mmc-ocr-mask = <3>;
uhs-mask = <0x0>;
tap-delay = <3>;
};

Hi,

What is your mmc1/ios info now?

Is cold boot and warm boot making any difference in the clk speed?

Could you paste your final dtb here?

tegra210-p3448-0002-p3449-0000-b00.dtb.txt (231.8 KB)

I attached my dtb file.( I chaged extension to txt becuase I can’t attach dtb file )
And My ios info is same as before. There’s no difference both cold/warm boot.

clock: 50000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don’t care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 2 (sd high-speed)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)

Hi,

Which release are you using? Have you tried other card as well?

Do you have a gpio as SDMMC_VDD_EN on your board design?

Hi @WayneWWW,

I’m using L4T 32.2.1.
I tried 2 types sd cards and I could see the same issue. Both sd cards support uhs speed.

And I’ll check SDMMC_VDD_EN on my board design and update it.

BTW, SDMMC_VDD_EN is necessary for enabling uhs mode?

Thanks,
Dongjin Ha.

Hi,

Actually, I would hope you could upgrade to rel-32.4.3 or at least rel-32.4.2.
It could guarantee you don’t need to install extra driver patch to your code but only the dts.

BTW, SDMMC_VDD_EN is necessary for enabling uhs mode?

May not be necessary but we suggest it should be present.

It would be better if you could post your updated schematic here.

Hi @WayneWWW,

Actually it’s not easy to upgrade l4t version in my case.
Could you let me know what specific properties need to be compared with latest l4t? ( SDMMC3? )

And do you think there’s no problem with my attached dtb file?

Yes, I think there is no problem

The only issue we resolved for sd slow speed is the patch you mentioned (9875882.diff) and remove “‘max-clk-limit” in dts.

And here is my schematic about micro sd card.
I can’t update whole schematic file, sorry. If you need to check other parts, tell mel.

Hi,

Could you check the device tree on device by check the node in /proc/device-tree?

This is to make sure your dtb loaded on the device is really same as the one you shared with us.

As you know, there are lots of bugs resolved after rel-32.3. One issue was that the dtb file may not updated correctly.

Thus, better checking the properties are really correct there.
What you need to do is go to /proc/device-tree/sdhci@700b0400 and review if everything matches your dtb.

Could you let me know how can I check the properties are really correct in my board?
When I check /proc/device-tree/sdhci@700b0400 , I can see below lists.

-r–r--r-- 1 root root 14 Jul 9 10:12 aux-device-name
-r–r--r-- 1 root root 4 Jul 9 10:12 bus-width
-r–r--r-- 1 root root 4 Jul 9 10:12 calib-1v8-offsets
-r–r--r-- 1 root root 4 Jul 9 10:12 calib-3v3-offsets
-r–r--r-- 1 root root 0 Jul 9 10:12 cap-mmc-highspeed
-r–r--r-- 1 root root 0 Jul 9 10:12 cap-sd-highspeed
-r–r--r-- 1 root root 12 Jul 9 10:12 cd-gpios
-r–r--r-- 1 root root 0 Jul 9 10:12 cd-inverted
-r–r--r-- 1 root root 40 Jul 9 10:12 clock-names
-r–r--r-- 1 root root 32 Jul 9 10:12 clocks
-r–r--r-- 1 root root 4 Jul 9 10:12 compad-vref-1v8
-r–r--r-- 1 root root 4 Jul 9 10:12 compad-vref-3v3
-r–r--r-- 1 root root 22 Jul 9 10:12 compatible
-r–r--r-- 1 root root 4 Jul 9 10:12 ddr-clk-limit
-r–r--r-- 1 root root 0 Jul 9 10:12 ignore-pm-notify
-r–r--r-- 1 root root 12 Jul 9 10:12 interrupts
-r–r--r-- 1 root root 8 Jul 9 10:12 iommus
-r–r--r-- 1 root root 4 Jul 9 10:12 linux,phandle
-r–r--r-- 1 root root 4 Jul 9 10:12 max-clk-limit
-r–r--r-- 1 root root 0 Jul 9 10:12 mmc-ddr-1_8v
-r–r--r-- 1 root root 4 Jul 9 10:12 mmc-ocr-mask
-r–r--r-- 1 root root 6 Jul 9 10:12 name
-r–r--r-- 1 root root 0 Jul 9 10:12 no-mmc
-r–r--r-- 1 root root 0 Jul 9 10:12 no-sdio
-r–r--r-- 1 root root 0 Jul 9 10:12 nvidia,cd-wakeup-capable
-r–r--r-- 1 root root 0 Jul 9 10:12 nvidia,en-io-trim-volt
-r–r--r-- 1 root root 0 Jul 9 10:12 nvidia,en-periodic-calib
-r–r--r-- 1 root root 4 Jul 9 10:12 nvidia,runtime-pm-type
-r–r--r-- 1 root root 0 Jul 9 10:12 nvidia,vmmc-always-on
-r–r--r-- 1 root root 4 Jul 9 10:12 phandle
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-0
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-1
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-2
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-3
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-4
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-5
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-6
-r–r--r-- 1 root root 4 Jul 9 10:12 pinctrl-7
-r–r--r-- 1 root root 171 Jul 9 10:12 pinctrl-names
-r–r--r-- 1 root root 18 Jul 9 10:12 pll_source
drwxr-xr-x 10 root root 0 Jul 9 10:12 prod-settings/
-r–r--r-- 1 root root 0 Jul 9 10:12 pwrdet-support
-r–r--r-- 1 root root 16 Jul 9 10:12 reg
-r–r--r-- 1 root root 6 Jul 9 10:12 reset-names
-r–r--r-- 1 root root 8 Jul 9 10:12 resets
-r–r--r-- 1 root root 0 Jul 9 10:12 sd-uhs-sdr104
-r–r--r-- 1 root root 0 Jul 9 10:12 sd-uhs-sdr12
-r–r--r-- 1 root root 0 Jul 9 10:12 sd-uhs-sdr25
-r–r--r-- 1 root root 0 Jul 9 10:12 sd-uhs-sdr50
-r–r--r-- 1 root root 5 Jul 9 10:12 status
-r–r--r-- 1 root root 4 Jul 9 10:12 tap-delay
-r–r--r-- 1 root root 4 Jul 9 10:12 trim-delay
-r–r--r-- 1 root root 4 Jul 9 10:12 uhs-mask
-r–r--r-- 1 root root 4 Jul 9 10:12 vmmc-supply
-r–r--r-- 1 root root 4 Jul 9 10:12 vqmmc-supply
-r–r--r-- 1 root root 0 Jul 9 10:12 wp-inverted

Hi,

You could check the value with command “xxd”.

For example,

xxd status should give you “okay”.

Hi @WayneWWW

Thank you for your kind explanations.
I checked some properties and I think it’s correct.

nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd uhs-mask
00000000: 0000 0000 …
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd vmmc-supply
00000000: 0000 0058 …X
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd mmc-ocr-mask
00000000: 0000 0003 …
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd uhs-mask
00000000: 0000 0000 …
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd tap-delay
00000000: 0000 0003 …
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd max-clk-limit
00000000: 0c28 cb00 .(…
nvidia@tegra-ubuntu:/proc/device-tree/sdhci@700b0400$ xxd sd-uhs-sdr104

Do you want to check other properties except above?