Some Jetson NANO Modules are booting fail on the custom board

Autonomous Machines Jetson & Embedded Systems Jetson Nano
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  1. Does the Jetson Nano Module have a BOOTING Configure Port Pin ?
    example) GPIO0: LOW, GPIO1:HIGH …

(Custom Board)
-. GPIO01: Pull-Down(LOW)
-. GPIO05; Pull-Up(HIGH)
-. GPIO06; Pull-Up(HIGH)
-. GPIO07: Pull-DownLOW
-. GPIO08: Floating
-. GPIO09: Pull-DownLOW
-. GPIO11: Pull-Down,Up(LOW/HIGH)
-. GPIO12: Pull-Down,Up(LOW/HIGH)
-. GPIO13: Pull-Down(LOW)

attached file is “GPIOs.gif” .

GPIOs
GPIOs565×504 23.7 KB

  1. we do not use “M.2 KEY E” Port. Is it related BOOTING ?
    (Custom Board)
    -. BT_M2_WAKE_AP: FLOTING Port
    -. M2_E_ALERT : FLOTING Port
    -. BT_M2_EN: pull-down(LOW)
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No. There are on such port pins. BT_M2_EN should be float too since it is not used.

And please note, for the ports shared between module and carrier, their power supply on carrier should be ON later after carrier_power_on enabled. That’s to make sure the pins status won’t be affected by carrier during power on.

You may check your design for that, for any unused pins, they should be float in general. For shared IO pins, make sure they are powered after module power on.

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We solved the problem “Not BOOTING ISSUE”.

NVIDIA have to think about “Booting Problem of jetson nano Semiconductor or Module”.

Now, we are going to find out " LSF0204 than Nvidia recommanded Component TXB0104 Level Shift".

20220701_Booting_Solution_93PIN_CUT.pptx (67.5 KB)

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Hi, is LSF0204 powered up before module? If so, I think the root cause is your design cause the pin status changed during power on. As said, the IO pins should be powered after module power on.

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20220701_Bootin_POwer_DC-DC_sequence.pptx (37.1 KB)

Custom Board Adaptor & DC-DC Power Sequence.

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Is there default pull-down on the pin of LSF0204 if it is not powered up earlier than module? Anyway, it looks like level shift affect the pin status, right?

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Jetson nano 93(SPI0_MISO) pin must LOW, During jetson nano first initial BOOTING.
(During Booting 93 pin checked +1.8V and connected LSF0204 Level shfit IC pin)
Maybe 93 pin is Hidden Booting Configure Pin???

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(During Booting 93 pin checked +1.8V and connected LSF0204 Level shfit IC pin)

As I said previously, the shared IO pins (including pin 93) status should not be affected during power on, so the level shift in your design should be power on after carrier_power_on signal.

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