Supported/recommended RTOS for Jetson Xavier

Is there any supported/recommended RTOS or Safety Linux OS for Jetson Xavier. I have found only for Jetson TX1/TX2?


Hi Arrfou, you may be interested in Concurrent Redhawk Linux. It is a realtime version of Linux built on the RHEL distribution that supports Jetson TX1/TX2 and Jetson AGX Xavier.

Also in upcoming JetPack 4.2.1 release, a FreeRTOS sample for the Cortex-R5 core on TX2 and Xavier will be available.

Thank you very much for your answer. Good to know that there is an upcoming FreeRTOS sample. I am looking for the features of the Jetson Family to support real-time safety-critical systems.


I am also looking for RTOS. I would like to know how can we use free RTOS in ARM A57 cores? Is it possible to use it by updating JetPack version? You were talking about Cortex-R5. As you know, Jetson TX2 does not have Cortex-R5. So i really don’t understand relationship between free RTOS and Arm A57.

By the way, do you have any idea about how to use OpenAMP, Jailhouse and bare metal in Jetson TX2? What are the differences between them and free RTOS.

Jetson TX2 has Cortex-R5 core, it’s connected to the low-level I/O such as CAN bus, I2C, SPI, and GPIO.
See this block diagram from the Parker Series SoC Technical Reference Manual (TRM):

The upcoming FreeRTOS reference implementation isn’t intended to run on the Cortex-A57 cores. That would preclude the use of GPU acceleration. However following the TRM, you could port it to the A57 cores, or other RTOS as well. But they would not have CUDA driver available.


I am also interested in using a RTOS on the TX2 and Xavier. Until now, as I know only options are Preempt RT patch and RedHawk product. With this update, we will able to use other RTOS too, right?

As mentioned other answer, is it true that using jailhouse also make possible work with RTOS on Jetsons?

No! The upcoming FreeRTOS is for the smaller Cortex-R5 cores that run various subsystems in the Tegra systems. Not the main A57 / Carmel 64-bit cores that run Ubuntu and talk to the GPU.

Hi snarky,

dusty sad :


I mean can we use other any RTOS on cortex R5 or it will only support FreeRTOS?

I imagine that you would be able to pick apart what the FreeRTOS sample code is doing, and then re-assemble that into some other RTOS. It’ll probably be some work. The question is whether there are “required” modules you “must” run on the RTOS kernel, for audio or power supervision or whatever, and whether those “required” required modules in that case are portable to other runtimes.

Are there any insights how to utilize or run example with RTOS of the latter jetpack release?
Reference found:
“Jetson Sensor Processing Engine (SPE) Developer Guide New … This developer guide addresses development of FreeRTOS-based firmware for SPE.”

where to find rtos related sources?
“TOP=<path to root directory where rt-aux-cpu-demo, hwinc and freertos related sources/directories” [ from tutorial]
is it meant to be of a file ? specifically of FreeRTOSV8.1.2 ?
or from ?

Hi Andrey1984,

where can I get the rt-aux-cpu-demo ?


you can find them at

dipenp, thank you for pointing out!

may be you know what is the right ending for the line instruction from

export CROSS_COMPILE=<path to installed cross compiler>/gcc-arm-none-eabi-4_8-2014q3/bin/arm-none-eabi-

it shouldn’t have the dash at the end, should it?

export CROSS_COMPILE=/home/nvidia//Downloads/l4t-rt/gcc-arm-none-eabi-4_8-2014q3/bin/arm-none-eabi-
arm-none-eabi-addr2line   arm-none-eabi-gcc-4.8.4   arm-none-eabi-nm
arm-none-eabi-ar          arm-none-eabi-gcc-ar      arm-none-eabi-objcopy
arm-none-eabi-as          arm-none-eabi-gcc-nm      arm-none-eabi-objdump
arm-none-eabi-c++         arm-none-eabi-gcc-ranlib  arm-none-eabi-ranlib
arm-none-eabi-c++filt     arm-none-eabi-gcov        arm-none-eabi-readelf
arm-none-eabi-cpp         arm-none-eabi-gdb         arm-none-eabi-size
arm-none-eabi-elfedit     arm-none-eabi-gprof       arm-none-eabi-strings
arm-none-eabi-g++         arm-none-eabi-ld          arm-none-eabi-strip
arm-none-eabi-gcc         arm-none-eabi-ld.bfd

which of the list above is the right ending?

FYI, eabi is for 32-bit. If you are compiling for Xavier, and not using 32-bit foreign architecture/compatibility, then this is wrong. EABI is a reference to an optional hardware floating point calling convention…on 32-bit it was optional.

“eabi” is a particular embedded ABI, but that’s proper for the Cortex-R cores that are targeted with the RTOS SDK.

The CROSS_COMPILE environment variable SHOULD end in a dash, because it’s prefixed to the name of the tool used, so “gcc” turns into “$(CROSS_COMPILE)gcc”

Follow exactly what document says. Dash at the ending is correct, build system will automatically find the right options from it.

thank you for the explanation!it got built to form of binaries.

could you explain what will be exact steps to implement GPIO Application (app/gpio-app.c) ?

Does it require both to edit:, ENABLE_GPIO_APP flag,


three files below?


or any of these two modifications ( either or three files)?
And could you remind how to “Compile device tree and flash the entire board to ensure that the SCR, gpio interrupt mapping and pinmux settings are flashed on the board.” What will be exact commands for it?
will the following line do the mentioned device tree build and fit for further flashing of the board?

make ARCH=arm64 O=$TEGRA_KERNEL_OUT -j<n>

let say I enabled


In the file "/l4t-rt/rt-aux-cpu-demo/soc/t18x/
and edited three files at “nvidia_sdk/JetPack_4.2.1_Linux_GA_P2888/Linux_for_Tegra/bootloader/tegra194-mb1-bct-scr-cbb-mini.cfg”
what’s next step? how to combine them and assemble somehow?

Modifications of all the files are necessary. For the device tree, kernel, flashing board part, follow below steps:

  1. Download kernel sources, from in the Sources section of the Jetson AGX and TX2 column
  2. All the necessary device tree files mentioned in the SPE developer guide should be in the hardware directory once you have extracted kernel sources from the downloaded public_sources.tbz2 file, find related dtsi/device tree files mentioned in the SPE developer guide and modify it
  3. make ARCH=arm64 O=$TEGRA_KERNEL_OUT dtbs; this step only compiles device tree files; for more information about the prerequisites before executing this steps i.e. settign up cross compile variable etc…, follow guide
  4. copy compiled device tree dtb files as mentioned in the step 6 of the above guide (from step 3 link to the guide)
  5. All the *.cfg files mentioned in the SPE developer guide, for example, tegra194-mb1-bct-scr-cbb-mini.cfg (which can be present at <>/Linux_for_Tegra/bootloader/t186ref/BCT/tegra194-mb1-bct-scr-cbb-mini.cfg), after modification, you do not have to do anything, it will be automatically taken care during flashing step

Once you have followed all the steps mentioned above, flashing command to flash entire board is as follows, flashing script can be found at /Linux_for_Tegra:

  1. Jetson Platform must be in recovery mode
  2. cd /Linux_for_Tegra
  3. sudo ./ jetson-tx2 or jetson-xavier mmcblk0p1