TEGRA_GPIO("port", "offset")?

Hi -

I’m trying to map a couple GPIO pins in a device tree and none of the documents I’ve read explain what values to use for the (“port”, “offset”).

Specifically I want to use gpio79 (physical pin 12) and gpio216 (physical pin 7) on the Jetson Nano B01 version.

How do I determine the port and offset values?

test {
        compatible = "gpio-test";
        status = "okay";
        test-name {
                test-gpios = <&gpio TEGRA_GPIO(??, ??) GPIO_ACTIVE_HIGH>,
                test-gpios = <&gpio TEGRA_GPIO(??, ??) GPIO_ACTIVE_HIGH>;
        };

Thanks
Jamie

I think I figured it out. What was confusing me was that the port value is a letter and corresponds to a number.

A = 0, B=1, C=2, D=3 … AA = 26, BB = 27 and so on.

Take that corresponding number and multiply it by 8.

Then add the offset and you’ll end up with the sysfs gpio number.

Example:
TEGRA_GPIO(BB, 0)
BB = 27
27 * 8 + 0 (no offset) = 216
Therefore TEGRA_GPIO(BB, 0) = gpio216

Another example:
TEGRA_GPIO(J, 7)
J = 9
9 * 8 + 7 = 79
Therefore TEGRA_GPIO(J, 7) = gpio79

To determine the device tree mapping from the physical pin number or signal side, look at the pinmux table, look for the Jetson Nano signal name that corresponds to the physical pin number then look at the GPIO column and the values after “GPIO#_P” should give you the (port, offset).

Example:
GPIO3_PBB.00 is TEGRA_GPIO(BB, 0)

Does this all sound correct?

Thanks
Jamie

Yep.

#define TEGRA_GPIO_PORT_A 0
#define TEGRA_GPIO_PORT_B 1
#define TEGRA_GPIO_PORT_C 2
#define TEGRA_GPIO_PORT_D 3
#define TEGRA_GPIO_PORT_E 4
#define TEGRA_GPIO_PORT_F 5
#define TEGRA_GPIO_PORT_G 6
#define TEGRA_GPIO_PORT_H 7
#define TEGRA_GPIO_PORT_I 8
#define TEGRA_GPIO_PORT_J 9
#define TEGRA_GPIO_PORT_K 10
#define TEGRA_GPIO_PORT_L 11
#define TEGRA_GPIO_PORT_M 12
#define TEGRA_GPIO_PORT_N 13
#define TEGRA_GPIO_PORT_O 14
#define TEGRA_GPIO_PORT_P 15
#define TEGRA_GPIO_PORT_Q 16
#define TEGRA_GPIO_PORT_R 17
#define TEGRA_GPIO_PORT_S 18
#define TEGRA_GPIO_PORT_T 19
#define TEGRA_GPIO_PORT_U 20
#define TEGRA_GPIO_PORT_V 21
#define TEGRA_GPIO_PORT_W 22
#define TEGRA_GPIO_PORT_X 23
#define TEGRA_GPIO_PORT_Y 24
#define TEGRA_GPIO_PORT_Z 25
#define TEGRA_GPIO_PORT_AA 26
#define TEGRA_GPIO_PORT_BB 27
#define TEGRA_GPIO_PORT_CC 28
#define TEGRA_GPIO_PORT_DD 29
#define TEGRA_GPIO_PORT_EE 30
#define TEGRA_GPIO_PORT_FF 31

#define TEGRA_GPIO(port, offset) \
	((TEGRA_GPIO_PORT_##port * 8) + offset)
1 Like

hello JamieBasil,

there’s GPIO header file to define the port numbers, it’s tegra-gpio.h for Nano series,
note, TX2 and Xavier were using different header file, they’re tegra186-gpio.h and tegra194-gpio.h respectively.
btw,
when calculate the GPIO numbers, you should also check the kernel messages for the allocate ranges.
Nano series is allocate gpiochip0 from 0-255.
for example,

$ dmesg | grep "registered GPIOs"
[    0.559180] gpiochip_setup_dev: registered GPIOs 0 to 255 on device: gpiochip0 (tegra-gpio)
[    0.611064] gpiochip_setup_dev: registered GPIOs 504 to 511 on device: gpiochip1 (max77620-gpio)

therefore, you don’t need to add offset for your GPIO pins,
so, the number of TEGRA_GPIO(J, 7) is… ((9 * 8) + 7) + 0 = 79


for your reference,
here’s another case on Jetson AGX Xavier.
for example,
the gpiochip0 is allocated from 288-511; gpiochip1 from 248-287.
you’ll need to add the allocate offsets if you’re calculating the GPIO number on Xavier series.

$ dmesg | grep "registered GPIOs"
[    0.891870] gpiochip_setup_dev: registered GPIOs 288 to 511 on device: gpiochip0 (tegra-gpio)
[    0.900348] gpiochip_setup_dev: registered GPIOs 248 to 287 on device: gpiochip1 (tegra-gpio-aon)
[    1.091072] gpiochip_setup_dev: registered GPIOs 240 to 247 on device: gpiochip2 (max77620-gpio)
1 Like

Thank you