I can receive data normally in mater mode.(At this point, tx2 outputs clock and frame signal, and my i2s is connected to FPGA. FPGA USES the clock and frame signal of tx2 to output data to tx2.The data is received correctly)
But when I call i2s into slave mode, that is, I want to receive data using external clock and frame signals, I can’t receive data.
Compared to the above mater mode, I only changed the MASTER bit of i2s_CTRL_0 register to be 0.
FPGA has output clock and frame signals to i2s CLK and LRCLK pins(I checked with oscilloscope).
I checked the pinmux(I am using i2s2),It should be right.
Bank: 0 Reg: 0x02434000 Val: 0x00000450 -> dap2_din_pc3
Bank: 0 Reg: 0x02434008 Val: 0x00000440 -> dap2_dout_pc2
Bank: 0 Reg: 0x02434010 Val: 0x00000440 -> dap2_fs_pc4
Bank: 0 Reg: 0x02434018 Val: 0x00000440 -> dap2_sclk_pc1
My question is whether i2s should be entered into slave mode when I want to receive data from the external clock and frame signal. What additional parameter configurations are required.