Hello,
What is the correct order of calls to functions tegra210_i2s_set_fmt、tegra210_i2s_hw_params and tegra210_i2s_rx_stop?
When I call function tegra210_i2s_rx_stop,it prints Failed at I20_RX sw reset.
What are the possible reasons?
Hello!
Yes typically, you will find that tegra210_i2s_set_fmt() is called once during boot, then tegra210_i2s_hw_params and tegra210_i2s_rx/tx_stop are called in the order when audio is playback/capture is started.
If the software reset fails, then implies that the I2S interface is not receiving a clock. The most common cause of this is when the codec is the bit-clock master and …
- The codec is not generating the bit-clock
- The Tegra I2S pinmux is not correct. The I2S pad needs to be configured for I2S mode and the input enable bit needs to be set.
The best way to check the pinmux is by …
$ sudo grep dap1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 0 Reg: 0x02431028 Val: 0x00000400 → dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000458 → dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000400 → dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000400 → dap1_sclk_pj0
In the above registers, we need …
- Bit 10 set (selects the pin as an SFIO and not GPIO)
- Bit 6 set for any pin that is an input
- Bits [0:1] not set to select the I2S function
Regards,
Jon
Hello!
I check the pinmux:
Bank: 0 Reg: 0x02431028 Val: 0x00000440 → dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000450 → dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000440 → dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000440 → dap1_sclk_pj0
I set the i2s interface to master mode, shouldn’t it be output clock and frame?
Hello!
If the Tegra I2S is the master, then yes it should be outputting the bit clock and frame-sync. Please note that in device-tree where the slave/master is configured, this is from the codec perspective and not the Tegra I2S. So if the Tegra I2S is the master, then you should have ‘bitclock-slave’ and ‘frame-slave’ as shown below …
$ $ ls -l /proc/device-tree/sound/nvidia,dai-link-1/
total 0
-r--r--r-- 1 root root 4 Jan 29 09:59 bclk_ratio
-r--r--r-- 1 root root 0 Jan 29 09:59 bitclock-noninversion
-r--r--r-- 1 root root 0 Jan 29 09:59 bitclock-slave
-r--r--r-- 1 root root 7 Jan 29 09:59 bit-format
-r--r--r-- 1 root root 4 Jan 29 09:59 codec-dai
-r--r--r-- 1 root root 9 Jan 29 09:59 codec-dai-name
-r--r--r-- 1 root root 4 Jan 29 09:59 cpu-dai
-r--r--r-- 1 root root 5 Jan 29 09:59 cpu-dai-name
-r--r--r-- 1 root root 4 Jan 29 09:59 format
-r--r--r-- 1 root root 0 Jan 29 09:59 frame-noninversion
-r--r--r-- 1 root root 0 Jan 29 09:59 frame-slave
-r--r--r-- 1 root root 0 Jan 29 09:59 ignore_suspend
-r--r--r-- 1 root root 16 Jan 29 09:59 link-name
-r--r--r-- 1 root root 4 Jan 29 09:59 linux,phandle
-r--r--r-- 1 root root 18 Jan 29 09:59 name
-r--r--r-- 1 root root 2 Jan 29 09:59 name-prefix
-r--r--r-- 1 root root 4 Jan 29 09:59 num-channel
-r--r--r-- 1 root root 4 Jan 29 09:59 phandle
-r--r--r-- 1 root root 4 Jan 29 09:59 srate
-r--r--r-- 1 root root 5 Jan 29 09:59 status
cat /proc/device-tree/sound/nvidia,dai-link-1/cpu-dai-name
I2S1
Did you update the pinmux to set the input-enable for the I2S pins? You never need to set the input-enable for dout as this is always an output. If you want Tegra to be the master then you should not set the input-enable bit for these pads.
Regards,
Jon
I haven’t made any changes to the device tree.If I want to change the pinmux for i2s1,Should I add pin configuration to i2s1 under the ahub node in tegra186-quill-common.dtsi?There is already a configuration for i2s3 under this node.
ahub {
i2s@2901200 {
nvidia,is-pinctrl = <1>;
pinctrl-names = “dap_active”, “dap_inactive”;
pinctrl-0 = <&i2s3_dap_active_state>;
pinctrl-1 = <>;
};
};
I have ‘bitclock-slave’ and ‘frame-slave’ as shown below.
ls -l /proc/device-tree/sound/nvidia,dai-link-1/
-r--r--r-- 1 root root 4 Jul 10 07:13 bclk_ratio
-r--r--r-- 1 root root 0 Jul 10 07:13 bitclock-noninversion
-r--r--r-- 1 root root 0 Jul 10 07:13 bitclock-slave
-r--r--r-- 1 root root 7 Jul 10 07:13 bit-format
-r--r--r-- 1 root root 4 Jul 10 07:13 codec-dai
-r--r--r-- 1 root root 9 Jul 10 07:13 codec-dai-name
-r--r--r-- 1 root root 4 Jul 10 07:13 cpu-dai
-r--r--r-- 1 root root 5 Jul 10 07:13 cpu-dai-name
-r--r--r-- 1 root root 4 Jul 10 07:13 format
-r--r--r-- 1 root root 0 Jul 10 07:13 frame-noninversion
-r--r--r-- 1 root root 0 Jul 10 07:13 frame-slave
-r--r--r-- 1 root root 0 Jul 10 07:13 ignore_suspend
-r--r--r-- 1 root root 16 Jul 10 07:13 link-name
-r--r--r-- 1 root root 4 Jul 10 07:13 linux,phandle
-r--r--r-- 1 root root 18 Jul 10 07:13 name
-r--r--r-- 1 root root 2 Jul 10 07:13 name-prefix
-r--r--r-- 1 root root 4 Jul 10 07:13 num-channel
-r--r--r-- 1 root root 4 Jul 10 07:13 phandle
-r--r--r-- 1 root root 4 Jul 10 07:13 srate
-r--r--r-- 1 root root 5 Jul 10 07:13 status
cat /proc/device-tree/sound/nvidia,dai-link-1/cpu-dai-name
I2S1
Which file does ‘bitclock-slave’ and ‘frame-slave’ work in, which registers are configured, and I looked for the entire kernel code and didn’t find ‘bitclock-slave’ or ‘frame-slave’.
Hello!
Before changing the pinmux, you should just check the pinmux configuration from userspace. For I2S1 you can check the pinmux registers by …
$ sudo grep dap1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 0 Reg: 0x02431028 Val: 0x00000400 -> dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000458 -> dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000400 -> dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000400 -> dap1_sclk_pj0
If you have the above then I2S1 should be enabled on the 40-pin header on TX2. If you want to understand the values above please refer to the PADCTL_AUDIO_DAP1_xxx registers in the Tegra X2 TRM.
You actually need to search for ‘bitclock-master’ and ‘frame-master’. You should find these in the kernel source file sound/soc/soc-core.c.
Regards,
Jon
I already have the following pinmux configuration.
$ sudo grep dap1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 0 Reg: 0x02431028 Val: 0x00000400 -> dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000450 -> dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000400 -> dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000400 -> dap1_sclk_pj0
Do you mean that if you have the above pinmux configuration, it will have the i2s0 clock and frame output on the on the 40-pin header?I didn’t get the clock and the frame signal.Do I need to do anything else?
Yes. However, you also need to ensure that you have mux’ed the ADMAIF to the I2S1. For example, to play a WAV files on I2S1 …
amixer -c tegrasndt186ref cset name="I2S1 Mux" "ADMAIF1"
aplay -D hw:tegrasndt186ref,0 <wavfile>
Regards,
Jon
Now i2s can output clock and frame signals.If I don’t use sound card drivers.
If I call tegra210_i2s_set_fmt、tegra210_i2s_hw_params and tegra210_i2s_rx_stop functions separately, can i2s output the clock? That is, I only configure i2s interface registers, can i2s output clock.
When I call function tegra210_i2s_rx_stop,it prints Failed at I20_RX sw reset.
What are the possible reasons?
I don’t see why not, but we only test in the context of the using the I2S driver with the full soundcard.
As mentioned in comment #2, the only case when I have encountered this error is when the I2S is not receiving a clock. Without seeing a register dump for the I2S interface it is not possible to see how the I2S port is being configured and if it is being done correctly. So a register dump can help here.
You should also check how the clocks are setup for the I2S interface by looking at the ‘/sys/kernel/debug/clk/clk_summary’ output.
Regards,
Jon
Hello!
Because our actual application is that i2s are only used to receive or output data, and must be continuous and must be able to control start and stop freely.(We also do our own driver on the audio interface on other platforms for requirements)
The current configuration of my i2s register is as follows
[ 3191.373536] reg[2901000] value=1
[ 3191.376871] reg[2901004] value=1
[ 3191.380271] reg[2901008] value=0
[ 3191.383749] reg[290100c] value=0
[ 3191.387135] reg[2901010] value=0
[ 3191.390513] reg[2901014] value=3
[ 3191.393900] reg[2901018] value=0
[ 3191.397266] reg[290101c] value=0
[ 3191.400621] reg[2901020] value=3117700
[ 3191.404548] reg[2901024] value=100
[ 3191.408072] reg[2901028] value=0
[ 3191.411421] reg[290102c] value=0
[ 3191.414781] reg[2901030] value=0
[ 3191.418152] reg[2901034] value=0
[ 3191.421518] reg[2901038] value=0
[ 3191.424861] reg[290103c] value=0
[ 3191.428224] reg[2901040] value=1
[ 3191.431564] reg[2901044] value=1
[ 3191.434905] reg[2901048] value=0
[ 3191.438236] reg[290104c] value=0
[ 3191.441597] reg[2901050] value=0
[ 3191.444913] reg[2901054] value=3
[ 3191.448245] reg[2901058] value=0
[ 3191.451581] reg[290105c] value=0
[ 3191.454904] reg[2901060] value=3117700
[ 3191.458762] reg[2901064] value=100
[ 3191.462284] reg[2901068] value=0
[ 3191.465623] reg[290106c] value=0
[ 3191.468935] reg[2901070] value=0
[ 3191.472280] reg[2901074] value=0
[ 3191.475615] reg[2901078] value=0
[ 3191.478941] reg[290107c] value=0
[ 3191.482274] reg[2901080] value=1
[ 3191.485601] reg[2901084] value=0
[ 3191.488910] reg[2901088] value=1
[ 3191.492227] reg[290108c] value=0
[ 3191.495543] reg[2901090] value=0
[ 3191.498859] reg[2901094] value=0
[ 3191.502185] reg[2901098] value=0
[ 3191.505505] reg[290109c] value=0
[ 3191.508814] reg[29010a0] value=1f000407
[ 3191.512737] reg[29010a4] value=1f
[ 3191.516140] reg[29010a8] value=0
[ 3191.519456] reg[29010ac] value=0
There must be a problem with the I2S_AXBAR_R/TX_SOFT_RESET register being soft reset all the time.I have only configured the i2s register now, so I don’t know whether the reason for the problem is because the register is configured incorrectly or because I need to configure registers other than i2s.
Hello!
Looking at the register dump that looks good to me. So now we should check the clocks to see exactly how fast the I2S is being clocked. Although the I2S clock rate is set during hw_params, it is possible that the actual rate is different to the requested if the parent clock cannot be divided down. Can you attach a dump of ‘/sys/kernel/debug/clk/clk_summary’ taken after you see the soft reset error?
Regards,
Jon
Hello,
The following is the clock information:
root@tegra-ubuntu:/home/nvidia# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
vi 0 0 409600000 0 0
*[ default_freq 0]
isp 0 0 768000000 0 0
*[ default_freq 0]
eqos_rx_input 1 1 0 0 0
*[ default_freq 0]
eqos_rx 1 1 0 0 0
*[ default_freq 0]
axi_cbb 1 1 172800000 0 0
*[ default_freq 0]
sce_cpu_nic 2 2 115200000 0 0
*[ default_freq 0]
se 0 0 601600000 0 0
*[ default_freq 0]
gpc2clk 1 1 0 0 0
*[ default_freq 0]
gpcclk 1 1 140250000 0 0
*[ default_freq 0]
sor1_pad_clkout 0 0 0 0 0
*[ default_freq 0]
i2s6_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s2_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s1_sync_input 0 0 64000 0 0
*[ default_freq 0]
i2s1_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dspk2_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dspk1_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic4_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic3_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic2_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic1_sync_clk 0 0 64000 0 0
*[ default_freq 0]
spdifin_sync_input 0 0 0 0 0
*[ default_freq 0]
spdif_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s6_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s2_sync_clk 0 0 0 0 0
*[ default_freq 0]
nvjpg 0 0 857600000 0 0
*[ default_freq 0]
nvenc 0 0 1164800000 0 0
*[ default_freq 0]
vic 0 0 1024000000 0 0
*[ default_freq 0]
nvdec 0 0 1203200000 0 0
*[ default_freq 0]
tsecb 0 0 716800000 0 0
*[ default_freq 0]
tsec 0 0 716800000 0 0
*[ default_freq 0]
emc 0 0 665600000 0 0
*[ default_freq 0]
osc 3 3 38400000 0 0
*[ default_freq 0]
usb2_hsic_trk 1 1 9600000 0 0
*[ default_freq 0]
hsic_trk 0 0 9600000 0 0
*[ default_freq 0]
usb2_trk 1 1 9600000 0 0
*[ default_freq 0]
spi2 1 1 38400000 0 0
*[ default_freq 0]
nafll_disp 0 0 0 0 0
*[ default_freq 0]
dflldisp_div 0 0 0 0 0
*[ default_freq 0]
pwm4 1 1 38400000 0 0
*[ default_freq 0]
clk_m 5 5 19200000 0 0
*[ default_freq 0]
hda2hdmicodec 1 1 19200000 0 0
*[ default_freq 0]
tach 0 0 1010526 0 0
*[ default_freq 0]
spi4 1 1 19200000 0 0
*[ default_freq 0]
spi1 1 1 19200000 0 0
*[ default_freq 0]
sor1 0 0 19200000 0 0
*[ default_freq 0]
nvdisplay_p2 0 0 19200000 0 0
*[ default_freq 0]
i2s6 0 0 19200000 0 0
*[ default_freq 0]
i2s5 0 0 19200000 0 0
*[ default_freq 0]
i2s4 0 0 19200000 0 0
*[ default_freq 0]
i2s3 0 0 19200000 0 0
*[ default_freq 0]
i2s2 0 0 19200000 0 0
*[ default_freq 0]
nvdisplay_p1 0 0 19200000 0 0
root@tegra-ubuntu:/home/nvidia# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
vi 0 0 409600000 0 0
*[ default_freq 0]
isp 0 0 768000000 0 0
*[ default_freq 0]
eqos_rx_input 1 1 0 0 0
*[ default_freq 0]
eqos_rx 1 1 0 0 0
*[ default_freq 0]
axi_cbb 1 1 172800000 0 0
*[ default_freq 0]
sce_cpu_nic 2 2 115200000 0 0
*[ default_freq 0]
se 0 0 601600000 0 0
*[ default_freq 0]
gpc2clk 1 1 0 0 0
*[ default_freq 0]
gpcclk 1 1 140250000 0 0
*[ default_freq 0]
sor1_pad_clkout 0 0 0 0 0
*[ default_freq 0]
i2s6_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s2_sync_input 0 0 0 0 0
*[ default_freq 0]
i2s1_sync_input 0 0 64000 0 0
*[ default_freq 0]
i2s1_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dspk2_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dspk1_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic4_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic3_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic2_sync_clk 0 0 64000 0 0
*[ default_freq 0]
dmic1_sync_clk 0 0 64000 0 0
*[ default_freq 0]
spdifin_sync_input 0 0 0 0 0
*[ default_freq 0]
spdif_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s6_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_clk 0 0 0 0 0
*[ default_freq 0]
i2s2_sync_clk 0 0 0 0 0
*[ default_freq 0]
nvjpg 0 0 857600000 0 0
*[ default_freq 0]
nvenc 0 0 1164800000 0 0
*[ default_freq 0]
vic 0 0 1024000000 0 0
*[ default_freq 0]
nvdec 0 0 1203200000 0 0
*[ default_freq 0]
tsecb 0 0 716800000 0 0
*[ default_freq 0]
tsec 0 0 716800000 0 0
*[ default_freq 0]
emc 0 0 665600000 0 0
*[ default_freq 0]
osc 3 3 38400000 0 0
*[ default_freq 0]
usb2_hsic_trk 1 1 9600000 0 0
*[ default_freq 0]
hsic_trk 0 0 9600000 0 0
*[ default_freq 0]
usb2_trk 1 1 9600000 0 0
*[ default_freq 0]
spi2 1 1 38400000 0 0
*[ default_freq 0]
nafll_disp 0 0 0 0 0
*[ default_freq 0]
dflldisp_div 0 0 0 0 0
*[ default_freq 0]
pwm4 1 1 38400000 0 0
*[ default_freq 0]
clk_m 5 5 19200000 0 0
*[ default_freq 0]
hda2hdmicodec 1 1 19200000 0 0
*[ default_freq 0]
tach 0 0 1010526 0 0
*[ default_freq 0]
spi4 1 1 19200000 0 0
*[ default_freq 0]
spi1 1 1 19200000 0 0
*[ default_freq 0]
sor1 0 0 19200000 0 0
*[ default_freq 0]
nvdisplay_p2 0 0 19200000 0 0
*[ default_freq 0]
i2s6 0 0 19200000 0 0
*[ default_freq 0]
i2s5 0 0 19200000 0 0
*[ default_freq 0]
i2s4 0 0 19200000 0 0
*[ default_freq 0]
i2s3 0 0 19200000 0 0
*[ default_freq 0]
i2s2 0 0 19200000 0 0
*[ default_freq 0]
nvdisplay_p1 0 0 19200000 0 0
Thanks. What kernel version are you using? This does not appear to be the v4.4 Linux kernel that is distributed with L4T rel28.x.
With L4T kernel I would expect to see a lot more clocks and there should be a ‘req_rate’ field along with the actual rate so you can see what is requested and what you are getting. For example, see …
Looking at the above apart from the ‘i2s1_sync_clk’ I don’t see the actual ‘i2s1’ clock but only clocks for i2s2-6. So it looks like a problem with how the clocks are setup.
Regards,
Jon
The kernel version is 27.1.
Should I configure registers other than I2S?What might be wrong with the clock setting?
I have flashed r27.1 and attached is a dump of the clocks from this release. You will see both a ‘i2s1’ and ‘i2s1_sync_xxxx’ clocks. I am not sure why you do not see these clocks, however, I assume that there must be changes you have made to device-tree and/or the kernel that prevents these clocks from being registered. If you flash the original r27.1 release you should see all these clocks. You need to isolate the changes that you have made that would be causing this.
Regards,
Jon
clk-summary.txt (29.2 KB)
Thank you very much for your patient answer.I need to compare the differences.Thank you very much.