Timestamps on JetPack 4.6


Our configuration is Jetson AGX Xavier DevKit with Camera Board LI-IMX390 by ConnectTech.

We flashed JetPack 4.6. After connected 2 LI-IMX390 cameras to J2 pins 1 and 2, only one LED lit up, which means that they are connected to one deserializer.

However, when we run 2 pipelines with nvarguscamerasrc, the frame timestamps are different.
And from launch to launch, sometimes the difference reaches only 1 ms, sometimes 16ms. Why is that?
We also corrected the nvarguscamerasrc code and get timestamp from iMetadata->getSensorTimestamp() instead of iFrame->getNumber(); but nothing changes.

In the same configuration but in version JetPack 4.4 the timestamps on the cameras are almost the same for example:


How can we synchronize 2 cameras in one serializer? We use this to build the camera disparity. And it is important for us that the timestamps are nearby.


Using getSensorSofTimestampTsc() to verify it.



ShaneCCC, thanks for your reply.

But we have different timestamp

iFrame->getTime() =                               2215763850000
iMetadata->getSensorTimestamp() =                 2215727908000
iSensorTimestampTsc->getSensorSofTimestampTsc() = 2220865493000
iSensorTimestampTsc->getSensorEofTimestampTsc() = 2220897841000

Why why does the timestamp (iMetadata) come earlier then Sof and Eof?
How to cast Sof and Eof to steady_clock and system_clock?

Have check below to transfer to system time.

Thank you.

But still use the method iSensorTimestampTsc->getSensorSofTimestampTsc() the timestamps are different for paired cameras.
The difference is from 0ms to 16ms. And when we restart the pipeline, it is always different.

Try boos the system to verify.

sudo nvpmodel -m 0
sudo jetson_clocks
sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee  /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate

Run the commands, log below.
But the timestamps are different.

sda@jetson:~$ sudo nvpmodel -m 0
sda@jetson:~$ sudo jetson_clocks
sda@jetson:~$ sudo su
root@jetson:/home/sda# echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
root@jetson:/home/sda# echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
root@jetson:/home/sda# echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
root@jetson:/home/sda# echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
root@jetson:/home/sda# cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
root@jetson:/home/sda# cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee  /sys/kernel/debug/bpmp/debug/clk/isp/rate
root@jetson:/home/sda# cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
root@jetson:/home/sda# cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate

Did you run the sync_sensor sample code?
Also does this sensor board have HW sync design?

But in the Jetpack 4.4 version, there are no such problems with the same equipment.