TIMING SPEC FOR PCIE 16X INTERFACE

[liubh5701023]

Is there a timing spec for the PCIe 8x slot relative signals:
SOC controls these signals.
PCIE_12V_EN_N module pin A59 GPIO05
PCIE_3V3_EN module pin L48 UART4_RX
PCIE5_CLKREQ_N module pin C8 PEX_L5_CLKREQ_N
PCIE5_RST_N module pin H10 PEX_L5_RST_N

[liubh5701023]

Update: For the CLK_req usage, is this pin necessary? The retimer
supplier suggests the clock can freely run to the retimer, with no clk req control. Is this suggestion workable?
Another question is that the initial time for the retimer is 2s, so the PCI reset should assert later 2s after the power is valid to the retimer chip? Is there a suggestion for the 2s delay to reset the retimer chip?

[sgursal]

Please refer to PCIe CEM Specification and PCIe Base Specification. With Common Clock architecture, CLKREQ_N is Optional. EMI issues will be reduced if clocks to open PCIe connectors are turned off at the clock source.

[sgursal]

We do not have timing spec for PCIe x8 slot. These parameters are system design dependent like choice of voltage regulators, voltage ramp up and stabilization time. Please refer to PCIe CEM specification for further guidance on relative timing for Power Up.

[liubh5701023]

From the timing spec: the reset_n is about 200ms from the first power rail on to the soc reset, but the pcie reset signal is from SOC, and pcie power rail is controlled by the pcie_3v3_EN and PCIE_12V_En_N, where can I adjust the timing for these 3 signals?