CLKREQ and RST pins for C7

what are the correct clkreq and reset pins for PCIE controller C7? by the pinmux there look like there could be two different sets:

Pins B36/B37 : PEX_C7__RST_N & PEX_C7_CLKREQ_N

or

Pins E11/D10 : PEX_C0_<function_name> but under ball name = GP188_PCIE7_RST_N & GP187_PCIE7_CLKREQ_N

please refer to the design guide document.

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