Hi Jon,
Thanks for the pointers, i’ve changed the clocks to 24.576MHz, essentially as follows for the 3.10 NVIDIA L4T kernel, resulting in the initialisation and maximum frequencies being updated:
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index 664d41c01278..5dbecc0a583f 100644
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -7085,8 +7085,8 @@ static struct clk tegra_pciex_clk = {
.dev_id = #_dev , \
.con_id = "ext_audio_sync", \
}, \
- .rate = 24000000, \
- .max_rate = 24000000, \
+ .rate = 24576000, \
+ .max_rate = 24576000, \
.ops = &tegra_sync_source_ops \
}
@@ -7137,7 +7137,7 @@ static struct clk_mux_sel mux_audio_sync_clk[] =
}, \
.inputs = mux_audio_sync_clk, \
.reg = 0x4A0 + (_index) * 4, \
- .max_rate = 24000000, \
+ .max_rate = 24576000, \
.ops = &tegra_audio_sync_clk_ops \
}
static struct clk tegra_clk_audio_list[] = {
@@ -7157,7 +7157,7 @@ static struct clk tegra_clk_audio_list[] = {
.con_id = "audio_sync_2x" \
}, \
.flags = PERIPH_NO_RESET, \
- .max_rate = 48000000, \
+ .max_rate = 49152000, \
.ops = &tegra_clk_double_ops, \
.reg = 0x49C, \
.reg_shift = 24 + (_index), \
(…25MHz was a typo in the previous post, indeed)
This seems to have cleared up a problem with the data not keeping in sync with the frame sync, so that looks a lot better. I can’t say it works 100% yet, because i haven’t managed to get verifiable data from I2S via ALSA, likely for other reasons. Although, with a logic analyser, the data on the bus seems correct, as far as i can tell.
To put it another way, I can’t tell whether the data is in fact being clocked in correctly by the I2S block at 25.576 MHz, but the data it’s sending looks ok.
Thanks,
Ed