Toshiba tc358840 No HDMI Sync

son.le · June 14, 2023, 10:08am

Hi

I am trying to bring up TC358840 to Xavier NX.
I use Jetson 5.02 (JetPack_5.0.2_Linux_JETSON_XAVIER_NX_TARGETS)

The problem is that the Toshiba chip always said that NO SYNC on HDMI in

12.437100] v4l2-ctrls: tc358840 2-000f: Power Present: 0x00000001
[ 12.437648] v4l2-ctrls: tc358840 2-000f: Splitter Width: 1920

[ 12.437963] tc358840 2-000f: -----Chip status-----

[ 12.453294] tegra-i2c 3190000.i2c: I2C transfer timed out
[ 12.462196] tc358840 2-000f: Chip ID: 0x47

[ 12.465899] tc358840 2-000f: Chip revision: 0x00
[ 12.466059] tc358840 2-000f: Reset: IR: 0, CEC: 0, CSI TX: 0, HDMI: 0
[ 12.466256] tc358840 2-000f: Sleep mode: off
[ 12.468786] tc358840 2-000f: Cable detected (+5V power): yes
[ 12.473574] tegra210-adsp tegra210-adsp: Loaded app adma

[ 12.497484] tc358840 2-000f: DDC lines enabled: yes
[ 12.497726] tc358840 2-000f: Hotplug enabled: no

[ 12.505186] tc358840 2-000f: CEC enabled: no
[ 12.506046] tc358840 2-000f: -----Signal status-----
[ 12.506571] tc358840 2-000f: TMDS signal detected: yes
[ 12.525579] tc358840 2-000f: Stable sync signal: no
[ 12.525731] tc358840 2-000f: PHY PLL locked: yes
[ 12.525887] tc358840 2-000f: PHY DE detected: yes

[ 12.529345] tegra210-adsp tegra210-adsp: Loaded app adma_tx

[ 12.534343] nvadsp_set_adma_dump_reg: callback for adma reg dump is sent to 00000000cd33d266
[ 12.555429] tegra210-adsp tegra210-adsp: Tegra210 ADSP driver successfully registered
[ 12.559506] get_detected_timings no sync on signal
[ 12.559704] tc358840 2-000f: No video detected
[ 12.565104] tc358840 2-000f: Configured format: 1920x1080p30.00 (2200x1125)
[ 12.573337] tegra-i2c 3190000.i2c: I2C transfer timed out
[ 12.590391] tc358840 2-000f: horizontal: fp = 88, +sync = 44, bp = 148
[ 12.590601] tc358840 2-000f: vertical: fp = 4, +sync = 5, bp = 36

12.590764] tc358840 2-000f: pixelclock: 74250000
[ 12.592854] tc358840 2-000f: flags (0x92): CAN_REDUCE_FPS CE_VIDEO HAS_CEA861_VIC
[ 12.600381] tc358840 2-000f: standards (0x1): CEA
[ 12.610164] tc358840 2-000f: CEA-861 VIC: 34
[ 12.610372] tc358840 2-000f: -----CSI-TX status-----
[ 12.621387] tc358840 2-000f: Lanes needed: 4
[ 12.645596] LTS3b i2c_rd
[ 12.653216] tc358840 2-000f: Lanes in use: 4
[ 12.653410] LTS3b i2c_rd
[ 12.656417] tc358840 2-000f: Splitter disabled
[ 12.656619] tc358840 2-000f: Color space: YCbCr 422 16-bit
[ 12.656798] LTS3b i2c_rd
[ 12.657467] tc358840 2-000f: -----HDMI status-----
[ 12.657674] tc358840 2-000f: HDCP encrypted content: no
[ 12.657895] tc358840 2-000f: Input color space: YCbCr 709 limited range
[ 12.665524] tc358840 2-000f: AV Mute: off
[ 12.668867] tc358840 2-000f: Deep color mode: 8-bits per channel

v4l2_async_register_subdev hdmi_sys_status=0x1F sysctl=0x0000 vi_status3= 0x07

==================================================================

My device-tree is as following:

===============================================================
/ {
host1x {

	vi_base: vi {
		num-channels = <1>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			tc_vi_port0: port@0 { /* HDMI IN A (4K) */
				reg = <0>;
				status = "okay"; 
				tc358840_vi_in0: endpoint {
					status = "okay";
					port-index = <0>;
					bus-width = <4>;
					//gang-mode = <1>;
					remote-endpoint = <&tc358840_csi_out0>;
				};
			};
		};
	};

	csi_base: nvcsi {
		num-channels = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		channel@0 {
			reg = <0>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					status = "okay"; 
					reg = <0>;
					tc358840_csi_in0: endpoint@0 {
						status = "okay";
						port-index = <0>; 
						bus-width = <4>;
						//gang-mode = <1>; /* MAY REMOVE */
						remote-endpoint = <&tc358840_out0>;
					};
				};
				port@1 {
					status = "okay"; 
					reg = <1>;
					tc358840_csi_out0: endpoint@1 {
						status = "okay";
						remote-endpoint = <&tc358840_vi_in0>;
					};
				};
			};
		};
	};
};

hdmi_osc: hdmi-osc {
compatible = “fixed-clock”;
clock-output-names = “hdmi-osc”;
clock-frequency = <48000000>;
#clock-cells = <0>;
};
/LTS************/
i2c@3180000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
status = “okay”;
vana-supply = <&p3509_avdd_cam_2v8>;
vif-supply = <&p3509_vdd_1v8_cvb>;
/* rework: also enables VDD_1V_SATA_PHY (1.18 V) */
vdig-supply = <&p3509_vdd_1v8_cvb>;

	/* HDMI IN A (4K) */
	tc358840@0f {
		compatible = "toshiba,tc358840";
		reg = <0x0f>;
		status = "okay";
		clocks = <&hdmi_osc>;
		clock-names = "refclk";
        devnode = "video0"; 
        /* Power Supply */
        vif-supply = <&p3509_vdd_1v8_cvb>;
        vdig-supply = <&p3509_vdd_1v8_cvb>;


		/* Sensor Model */
		sensor_model ="tc358840";

		/* Physical dimensions of sensor */
		physical_w = "4.713";
		physical_h = "3.494";

		/* GPIO */
		reset-gpio = <&tegra_main_gpio ENA_RST GPIO_ACTIVE_HIGH>;
		reset-cam = <&tegra_main_gpio CAM2_RST GPIO_ACTIVE_LOW>;
		ena_5v-gpio = <&tegra_main_gpio ENA_5V GPIO_ACTIVE_HIGH>;


		/* Interrupt */
		interrupt-parent = <&tegra_main_gpio>;
        		interrupts = <TC358840_INT GPIO_ACTIVE_HIGH>;

		refclk_hz = <48000000>; /* 40 - 50 MHz */

		ddc5v_delay = <1>; 

		/* HDCP */
		enable_hdcp = <0>;

		/* CSI Output */
		csi_port = <3>;

		lineinitcnt = <0x00000FA0>;
		lptxtimecnt = <0x00000004>;
		tclk_headercnt = <0x00180203>;
		tclk_trailcnt = <0x00040005>;
		ths_headercnt = <0x000D0004>;
		twakeup = <0x00003E80>;
		tclk_postcnt = <0x0000000A>;
		ths_trailcnt = <0x00080006>;
		hstxvregcnt = <0x00000020>;
		btacnt =  <0>;

	/* PLL */
		/* Bps per lane is (refclk_hz / pll_prd) * pll_fbd */
		pll_prd = <10>;//9+1
		pll_fbd = <125>;//124+1
		pll_frs = <1>;

mode0 {
mclk_khz = “24000”;
num_lanes = “4”;
tegra_sinterface = “serial_a”;
phy_mode = “DPHY”;
discontinuous_clk = “yes”;
dpcm_enable = “false”;
cil_settletime = “0”;

			active_w = "1920";
			active_h = "1080";
			mode_type = "rggb";
			readout_orientation = "0";
			line_length = "2200";
			inherent_gain = "1";

			mclk_multiplier = "25";
			pix_clk_hz = "74250000";

			min_gain_val = "1";
			max_gain_val = "16";
			min_hdr_ratio = "1";
			max_hdr_ratio = "64";
			min_framerate = "1000000";
			max_framerate = "30000000";
			default_framerate = "30000000";
			min_exp_time = "30";        // us 
			max_exp_time = "660000";    // us
			embedded_metadata_height = "1";

			dynamic_pixel_bit_depth = "24";
			csi_pixel_bit_depth = "24";
			gain_factor = "10";
			step_gain_val = "3";        // 0.3
			default_gain = "1";
			step_framerate = "1";
			framerate_factor = "1000000";
			step_exp_time = "1";
			default_exp_time = "33334"; // us
		};

ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tc358840_out0: endpoint {
port-index = <0>;
bus-width = <4>;

                    data-lanes = <1 2 3 4>;
                    clock-lanes = <0>;
					remote-endpoint = <&tc358840_csi_in0>;
				};
			};
		};
	};
};

=================================================================

ShaneCCC · June 19, 2023, 1:37am

Did you confirm the i2c communication with tc358840?

ltson36 · June 19, 2023, 7:52am

HI

tegra-i2c 3190000.i2c: I2C transfer timed out

This is not I2C to TC358840, as the address is 3190000. I think it is the address of HDMI out port, and because it is not connected, so it shows error.

The TC358840 uses the address 31800000, and it has I2C work fine. From the log, it could read Chip ID, etc, and it does not show error in other read/write processes.

ShaneCCC · June 20, 2023, 1:01pm

Looks like read the 0x8520 status REG for the MASK_SYNC bit failed.

ltson36 · June 20, 2023, 1:11pm

Hi
From TC358840 doc:

SYS STATUS (SYS_STATUS) (0x8520)
S_SYNC 7
Input Video sync signal status
0: No sync signal (unstable)
1: With sync signal (stable)
Note: For the generation conditions for this status, follow the address
0x85C5 to 0x85CD settings

When it reads S_SYNC bit, it reports NO_SYNC, that why in log message it shows no sync signal.

ShaneCCC · June 20, 2023, 1:52pm

Maybe check the datasheet for the detail information.

system · July 18, 2023, 5:45am

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Toshiba tc358840 No HDMI Sync

The problem is that the Toshiba chip always said that NO SYNC on HDMI in

Hi From TC358840 doc:

SYS STATUS (SYS_STATUS) (0x8520) S_SYNC 7 Input Video sync signal status 0: No sync signal (unstable) 1: With sync signal (stable) Note: For the generation conditions for this status, follow the address 0x85C5 to 0x85CD settings

Related topics

Hi
From TC358840 doc:

SYS STATUS (SYS_STATUS) (0x8520)
S_SYNC 7
Input Video sync signal status
0: No sync signal (unstable)
1: With sync signal (stable)
Note: For the generation conditions for this status, follow the address
0x85C5 to 0x85CD settings