TC358743 on TX1 problem

Autonomous Machines Jetson & Embedded Systems Jetson TX1
1

Hi, all

We use tc358743 device on TX1, i meet any problem when testing.
JetPack: 3.0
tc358743: 1080p60, bps_per_lane: 594M, lanes: 4.
following message

[ 1999.417635] vi vi: Failed to get clock vi.
[ 1999.425438] tc358743 6-000f: HDMI Detected Image Size 1920x1080
[ 1999.969478] Host read timeout at address 54080908
[ 1999.970718] tc358743 6-000f: -----Chip status-----
[ 1999.970721] tc358743 6-000f: State: SR2
[ 1999.970723] tc358743 6-000f: Reset: IR: 0, CEC: 0, CSI TX: 0, HDMI: 0
[ 1999.970724] tc358743 6-000f: Sleep mode: off
[ 1999.970725] tc358743 6-000f: Cable detected (+5V power): yes
[ 1999.970934] tc358743 6-000f: DDC lines enabled: no
[ 1999.971140] tc358743 6-000f: Hotplug enabled: yes
[ 1999.971368] tc358743 6-000f: CEC enabled: no
[ 1999.971369] tc358743 6-000f: -----Signal status-----
[ 1999.971370] tc358743 6-000f: TMDS signal detected: yes
[ 1999.971371] tc358743 6-000f: Stable sync signal: yes
[ 1999.971373] tc358743 6-000f: PHY PLL locked: yes
[ 1999.971374] tc358743 6-000f: PHY DE detected: yes
[ 1999.971375] tc358743 6-000f: -----CSI-TX status-----
[ 1999.971376] tc358743 6-000f: Waiting for particular sync signal: no
[ 1999.971377] tc358743 6-000f: Transmit mode: yes
[ 1999.971378] tc358743 6-000f: Stopped: no
[ 1999.971378] tc358743 6-000f: HDCP encrypted content: no
[ 2001.967950] vi vi: CSI 0 syncpt timeout, syncpt = 7, err = -11
[ 2002.477477] Host read timeout at address 54080a5c
[ 2002.482590] vi vi: TEGRA_CSI_DEBUG_COUNTER 0xffffffff
[ 2002.990660] vi vi: TEGRA_CSI_CSI_CIL_STATUS 0xffffffff
[ 2002.990744] Host read timeout at address 5408093c
[ 2003.503275] vi vi: TEGRA_CSI_CSI_CILX_STATUS 0xffffffff
[ 2003.503370] Host read timeout at address 54080940
[ 2004.015765] vi vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0xffffffff
[ 2004.015905] Host read timeout at address 54080854
[ 2004.017120] vi vi: MW_ACK_DONE syncpoint time out!
[ 2004.533804] vi vi: TEGRA_VI_CSI_ERROR_STATUS 0xffffffff
[ 2004.533925] Host read timeout at address 54080184
[ 2006.537967] vi vi: CSI 0 syncpt timeout, syncpt = 7, err = -11
[ 2007.047296] Host read timeout at address 54080a5c
[ 2007.050149] vi vi: TEGRA_CSI_DEBUG_COUNTER 0xffffffff
[ 2007.555778] vi vi: TEGRA_CSI_CSI_CIL_STATUS 0xffffffff
[ 2008.059678] vi vi: TEGRA_CSI_CSI_CILX_STATUS 0xffffffff
[ 2008.563003] vi vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0xffffffff
[ 2009.066096] vi vi: TEGRA_VI_CSI_ERROR_STATUS 0xffffffff
[ 2009.081948] vi vi: MW_ACK_DONE syncpoint time out!
[ 2011.057844] vi vi: CSI 0 syncpt timeout, syncpt = 7, err = -11
[ 2011.567663] Host read timeout at address 54080a5c
[ 2011.570674] vi vi: TEGRA_CSI_DEBUG_COUNTER 0xffffffff
[ 2012.073331] vi vi: TEGRA_CSI_CSI_CIL_STATUS 0xffffffff
[ 2012.576212] vi vi: TEGRA_CSI_CSI_CILX_STATUS 0xffffffff
[ 2013.078859] vi vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0xffffffff
[ 2013.581541] vi vi: TEGRA_VI_CSI_ERROR_STATUS 0xffffffff
[ 2013.599991] vi vi: MW_ACK_DONE syncpoint time out!

How can i check and settle the problem?

Thanks & Best regards!

Richard, 2017-9-6

2

It’s should tegra CSI can’t get/decoder frame from the mipi bus. You may need to probe the mipi signal to make sure the signal is mipi compliance first.

3

Hi, all
i test tc358743 on tx1, use e3326(ov5693) device tree as module, e3326 work well, but tc358743 can not found subdev.
if i write device tree, how modify kernel source code ?

tegra210-camera-e3326-a01.dtsi:
/ {
host1x {
vi {
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_vi_in0: endpoint {
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3326_vo_out0>;
};
};
};
};

	i2c@546c0000 {
		status = "okay";
		#address-cells = <1>;
		#size-cells = <0>;
		tc358743@0f {
			compatible = "toshiba,tc358743";
			reg = <0x0f>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					reg = <0>;
					e3326_vo_out0: endpoint {
						remote-endpoint = <&e3326_vi_in0>;
					};
				};
			};
		};
	};
};

tegra-camera-platform {
	compatible = "nvidia, tegra-camera-platform";
	modules {
		module0 {
			badge = "e3326_front_P5V27C";
			position = "rear";
			orientation = "1";
			drivernode0 {
				/* Declare PCL support driver (classically known as guid)  */
				pcl_id = "v4l2_sensor";
				/* Driver's v4l2 device name */
				devname = "tc358743 6-000f";
				/* Declare the device-tree hierarchy to driver instance */
				proc-device-tree = "/proc/device-tree/host1x/i2c@546c0000/tc358743@0f";
			};
		};
	};
};

};

tegra210-jetson-cv-camera-e3326-a01.dtsi
/ {
tegra-camera-platform {
compatible = “nvidia, tegra-camera-platform”;
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <2>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <2>;
isp_bw_margin_pct = <25>;
};

host1x {
	i2c@546c0000 {
		tc358743@0f {
			/* Define any required hw resources needed by driver */
			/* ie. clocks, io pins, power sources */
			/* mclk-index indicates the index of the */
			/* mclk-name with in the clock-names array */
			clocks = <&tegra_car TEGRA210_CLK_ID_CLK_OUT_3>;
			clock-names = "mclk";
			clock-frequency = <24000000>;
			
			mclk = "cam_mclk1";
			reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
			pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
		};
	};
};

gpio: gpio@6000d000 {
	camera-control {
		gpio-output-low = <
			CAM0_RST_L
			CAM0_PWDN
			>;
	};
};

};

tegra210-jetson-cv-camera-modules.dtsi
/ {
/* set camera gpio direction to output /
/ gpio: gpio@6000d000 {
camera-control {
gpio-output-low = <
CAM0_RST_L
CAM0_PWDN
CAM1_RST_L
CAM1_PWDN
>;
};
};/
/ all cameras are disabled by default */
host1x {
i2c@546c0000 {
/e3326_cam0: ov5693_c@36 {
status = “disabled”;
};/
e3326_cam0: tc358743@0f {
status = “disabled”;
};
};
};
};

if not correct, how to modify?

Thanks and best regards!

Richard, 2017-09-12

4

Please download the document from below link and check the sensor programing guide.

https://developer.nvidia.com/embedded/dlc/l4t-documentation-28-1

5

Hi, ShaneCCC
In our design, tc358743 receives 1080p60 YUV data via HDMI,and sends to TX1, TX1 use 2 ports(A & B) to receive video data, each port use 2 lanes.
So, how to write device tree for the use case?

Thanks and Best regards!

2017-09-28

6

@Richard
You should reference to the sensor programing guide chapter “Using Main Platform Device Tree File” to implement your device tree.

7

Hi, all

TC358743 can be probed,but on TX1 side, I meet the following message:
…
[ 1140.495260] tegra_mipi_cal 700e3000.mipical: Mipi cal timeout,val:114880, lanes:300000
…

In our application:

HDMI–>TC358743–>CSI2

Jetpack : 3.0
Kernel : 3.10.96
Original : kernel4.4/driver/media/i2c/tc358743.c
In format : UYVY, up 1080p60
CSI cfg : CSI-A, 4 x lanes@594 MHz, no code modified.
Test tool : yatva
Chip cfg : ref. TC358743XBG_HDMI-CSI_Tv19p_nm.xls

I want to know, what’s meaning, and how to settle it?

Thanks & Best regards!

2017/10/13

8

How to adjust CSI timing on TX1 side ro meat custom use?

9

You can fine tune the settle time by modify the REG TEGRA_CSI_CIL_PHY_CONTROL, current it’s hard code as 0xA, You can check the TRM for detail information. However you need to make sure the output signal is mipi compliance first otherwise it’s useless.

int csi2_start_streaming(struct tegra_csi_channel *chan,
                                enum tegra_csi_port_num port_num)
{
        struct tegra_csi_port *port = &chan->ports[port_num];
        int csi_port, csi_lanes;

        csi_port = chan->ports[port_num].num;
        csi_lanes = chan->ports[port_num].lanes;

        csi_write(chan, TEGRA_CSI_CLKEN_OVERRIDE, 0, csi_port >> 1);

        /* Clean up status */
        pp_write(port, TEGRA_CSI_PIXEL_PARSER_STATUS, 0xFFFFFFFF);
        cil_write(port, TEGRA_CSI_CIL_STATUS, 0xFFFFFFFF);
        cil_write(port, TEGRA_CSI_CILX_STATUS, 0xFFFFFFFF);

        cil_write(port, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);

        /* CIL PHY registers setup */
        cil_write(port, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0);
        cil_write(port, TEGRA_CSI_CIL_PHY_CONTROL,
                        BYPASS_LP_SEQ | 0xA);

        /*
         * The CSI unit provides for connection of up to six cameras in
         * the system and is organized as three identical instances of
         * two MIPI support blocks, each with a separate 4-lane
         * interface that can be configured as a single camera with 4
         * lanes or as a dual camera with 2 lanes available for each
         * camera.
         */
        if (csi_lanes == 4) {
                unsigned int cilb_offset;

                cilb_offset = TEGRA_CSI_CIL_OFFSET + TEGRA_CSI_PORT_OFFSET;

                cil_write(port, TEGRA_CSI_CIL_PAD_CONFIG0,
                                BRICK_CLOCK_A_4X);
                csi_write(chan, cilb_offset + TEGRA_CSI_CIL_PAD_CONFIG0, 0x0,
                                csi_port >> 1);
                csi_write(chan, cilb_offset + TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0,
                                csi_port >> 1);
                cil_write(port, TEGRA_CSI_CIL_PHY_CONTROL,
                                BYPASS_LP_SEQ | 0xA);
                csi_write(chan, cilb_offset + TEGRA_CSI_CIL_PHY_CONTROL,
                                BYPASS_LP_SEQ | 0xA, csi_port >> 1);
                csi_write(chan, TEGRA_CSI_PHY_CIL_COMMAND,
                                CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE,
                                csi_port >> 1);
        } else {
                u32 val = csi_read(chan, TEGRA_CSI_PHY_CIL_COMMAND,
                                        csi_port >> 1);
10

Hi every one.

Currently i can connect B102 with J100 and get data 720P60 from it with RGB color space but now i want to config B102 output with YV12 color space for shorter capture time. When i tried to change color space to YV12 in driver, i only grabbed still image, not video. Have any one meet this situation before. Please help me?