Updating Pinmux Config Without Flashing

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hello!

I need to update my Jetson TX2s pinmux configuration. I can’t access to TX2 physically at the moment but have remote connection. TX2 has Jetpack 4.4.1 on it.

I saw topics related to editing pinmux on device. My problem occurs at the startup, so I need a complete update to pinmux configuration to have the changes at the startup.

Since I dont have access to device now, I need to update it remotely. Is there any way to do this?
How does this pinmux configuration stored in module?

Thanks in advance.

2

Actually, if you just want the pinmux to take effect in kernel. Then replacing the dtb should be sufficient.

3

Thanks for your reply.

Using pinmux spreadsheet I generate a .cfg file and place it in Linux_for_Tegra package. After flashing TX2 with this, generated pinmux applies. How can I generate new dtb including this pinmux configuration?

4

If you just want it take effect in kernel, then no need that cfg, the dts file from the spreadsheet is what we need.

5

Hello again,

Sorry for the late response.

Actually I couldn’t figured out how to use dts file that spreadsheet created. I have my custom dtb file with other modifications and I load it to TX2 using extlinux. In dts file we created with spreadsheet, there is only “pinmux@2430000” node present. So I decompile my custom dtb to dts file and add my desired pin block to “pinmux@2430000” node, under the common block.

To explain it better;
this is what I want to add to pinmux:

  	uart7_tx_pw6 {
  		nvidia,pins = "uart7_tx_pw6";
  		nvidia,function = "rsvd1";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  		nvidia,lpdr = <TEGRA_PIN_DISABLE>;
  	};

I want this pin “uart7_tx_pw6” to be out and drive 1 at the startup.

This pinmux node below is from my active custom dtb file. I added the block above to this node as this:

pinmux@2430000 {
        compatible = "nvidia,tegra186-pinmux";
        status = "okay";
        phandle = <0x9e>;
        reg = <0x0 0x2430000 0x0 0x15000 0x0 0xc300000 0x0 0x4000>;
        pinctrl-0 = <0x1e>;
        #gpio-range-cells = <0x3>;
        linux,phandle = <0x9e>;
        pinctrl-names = "default";

        vbus_en1_oc_passthrough {
                phandle = <0x8e>;
                linux,phandle = <0x8e>;

                usb_vbus_en1_pl5 {
                        nvidia,enable-input = <0x1>;
                        nvidia,pins = "usb_vbus_en1_pl5";
                        nvidia,tristate = <0x0>;
                        nvidia,io-high-voltage = <0x1>;
                        nvidia,function = "usb";
                };
        };

…

        common {
                phandle = <0x1e>;
                linux,phandle = <0x1e>;

                gpio_edp2_pp5 {
                        nvidia,enable-input = <0x1>;
                        nvidia,pins = "gpio_edp2_pp5";
                        nvidia,tristate = <0x1>;
                        status = "okay";
                        nvidia,pull = <0x2>;
                };

                #This is the block I added manually
                uart7_tx_pw6 {
                        nvidia,enable-input = <0x0>;
                        nvidia,pins = "uart7_tx_pw6";
                        nvidia,lpdr = <0x0>;
                        nvidia,tristate = <0x0>;
                        nvidia,function = "rsvd1";
                        nvidia,pull = <0x0>;
                };
               # 

                gpio_edp3_pp6 {
                        nvidia,enable-input = <0x0>;
                        nvidia,pins = "gpio_edp3_pp6";
                        nvidia,tristate = <0x0>;
                        status = "okay";
                        nvidia,pull = <0x0>;
                };
        };

…

};

I rebuilt dtb from dts with the modification above. Load it on TX2 but I couldn’t get my pin to start as out and drive 1.

Is this the correct way to add my pin configuration? How can I correct this?

6

Maybe you can firstly clarify on device node /proc/device-tree and search if your change in DTB is correct loaded.

7

I see that node is added. This path is present:
/proc/device-tree/pinmux@2430000/common/uart7_tx_pw6

Also I have these inside:
/proc/device-tree/pinmux@2430000/common/uart7_tx_pw6$ ls
name nvidia,enable-input nvidia,function nvidia,lpdr nvidia,pins nvidia,pull nvidia,tristate

I think it is applied. But I cant get the reaction I need. Are these settings correct for having the pin out and drive 1?

8

I don’t have those tools now so below comment is just my experience.

If you are saying that you want this pin to be configured as gpio, direction to “output” and default value is high. Then those settings in pinmux@2430000 is not sufficient.

I remember there should be 3 output files and one of them has some content “gpio” in it. It should define some gpio to output-low, and output-high state. You need to add that one too.

9

The conclusion of this post is wrong. Sorry about that. Need to flash the board.

Only cboot dtb is able to change the pinmux setting.